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參數(shù)資料
| 型號(hào)： | AD565ATQ |
| 英文描述： | 12-Bit Digital-to-Analog Converter |
| 中文描述： | 12位數(shù)字到模擬轉(zhuǎn)換器 |
| 文件頁數(shù)： | 4/11頁 |
| 文件大?。?/td> | 152K |
| 代理商： | AD565ATQ |
AD566A–SPECIFICATIONS
AD566AJ
Typ
AD566AK
Typ
Model
DATA INPUTS
1
(Pins 13 to 24)
TTL or 5 Volt CMOS
Input Voltage
Bit ON Logic “1”
Bit OFF Logic “0”
Logic Current (Each Bit)
Bit ON Logic “1”
Bit OFF Logic “0”
RESOLUTION
OUTPUT
Current
Unipolar (All Bits On)
Bipolar (All Bits On or Off)
Resistance (Exclusive of Span Resistors)
Offset
Unipolar (Adjustable to Zero per Figure 3)
Bipolar (Figure 4, R1 and R2 = 50
Fixed)
Capacitance
Compliance Voltage
T
MIN
to T
MAX
ACCURACY (Error Relative to
Full Scale) +25
°
C
Min
Max
Min
Max
Units
+2.0
0
+5.5
+0.8
+2.0
0
+5.5
+0.8
V
V
+120
+35
+300
+100
12
+120
+35
+300
+100
12
μ
A
μ
A
Bits
–1.6
0.8
6
–2.0
±
1.0
8
–2.4
1.2
10
–1.6
0.8
6
–2.0
±
1.0
8
–2.4
1.2
10
mA
mA
k
0.01
0.05
25
0.05
0.15
0.01
0.05
25
0.05
0.1
% of F.S. Range
% of F.S. Range
pF
–1.5
+10
–1.5
+10
V
±
1/4
(0.006)
±
1/2
(0.012)
1/2
±
1/8
(0.003)
±
1/4
(0.006)
1/4
LSB
% of F.S. Range
LSB
% of F.S. Range
(0.012)
3/4
(0.018)
(0.006)
1/2
(0.012)
T
MIN
to T
MAX
DIFFERENTIAL NONLINEARITY
+25
°
C
T
MIN
to T
MAX
TEMPERATURE COEFFICIENTS
Unipolar Zero
Bipolar Zero
Gain (Full Scale)
Differential Nonlinearity
SETTLING TIME TO 1/2 LSB
All Bits ON-to-OFF or OFF-to-ON (Figure 8)
FULL-SCALE TRANSITION
10% to 90% Delay plus Rise Time
90% to 10% Delay plus Fall Time
POWER REQUIREMENTS
V
EE
, –11.4 to –16.5 V dc
POWER SUPPLY GAIN SENSITIVITY
2
V
EE
= –11.4 to –16.5 V dc
PROGRAMMABLE OUTPUT RANGES
(see Figures 3, 4, 5)
±
1/2
3/4
±
1/4
1/2
LSB
MONOTONICITY GUARANTEED
MONOTONICITY GUARANTEED
1
5
7
2
2
10
10
1
5
3
2
2
10
5
ppm/
°
C
ppm/
°
C
ppm/
°
C
ppm/
°
C
250
350
250
350
ns
15
30
30
50
15
30
30
50
ns
ns
–12
–18
–12
–18
mA
15
25
15
25
ppm of F.S./%
0 to +5
–2.5 to +2.5
0 to +10
–5 to +5
–10 to +10
0 to +5
–2.5 to +2.5
0 to +10
–5 to +5
–10 to +10
V
V
V
V
V
EXTERNAL ADJUSTMENTS
Gain Error with Fixed 50
Resistor for R2 (Figure 3)
Bipolar Zero Error with Fixed
50
Resistor for R1 (Figure 4)
Gain Adjustment Range (Figure 3)
Bipolar Zero Adjustment Range
REFERENCE INPUT
Input Impedance
POWER DISSIPATION
MULTIPLYING MODE PERFORMANCE (All Models)
Quadrants
Reference Voltage
Accuracy
Reference Feedthrough (Unipolar Mode,
All Bits OFF, and 1 V to +10 V [p-p], Sine Wave
Frequency for 1/2 LSB [p-p] Feedthrough)
Output Slew Rate 10%–90%
90%–10%
Output Settling Time (All Bits ON and a 0 V–10 V
Step Change in Reference Voltage)
CONTROL AMPLIFIER
Full Power Bandwidth
Small-Signal Closed-Loop Bandwidth
NOTES
1
The digital input levels are guaranteed but not tested over the temperature range.
2
The power supply gain sensitivity is tested in reference to a V
EE
of –1.5 V dc.
Specifications subject to change without notice.
±
0.1
0.25
±
0.1
0.25
% of F.S. Range
±
0.05
0.15
±
0.05
0.1
% of F.S. Range
% of F.S. Range
% of F.S. Range
±
0.25
±
0.15
±
0.25
±
0.15
15
20
180
25
300
15
20
180
25
300
k
mW
Two (2): Bipolar Operation at Digital Input Only
+1 V to +10 V, Unipolar
10 Bits (
±
0.05% of Reduced F.S.) for 1 V dc Reference Voltage
40 kHz typ
5 mA/
μ
s
1 mA/
μ
s
1.5
μ
s to 0.01% F.S.
300 kHz
1.8 MHz
(T
A
= +25 C, V
EE
= –15 V, unless otherwise noted)
–4–
REV. D
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