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參數(shù)資料
| 型號： | AD5626BRMZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC NANO 12BIT 8-MSOP |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 50 |
| 系列： | nanoDAC™ |
| 設(shè)置時間： | 16µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 12.5mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-MSOP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | * |
AD5626
Rev. A | Page 12 of 20
APPLICATIONS INFORMATION
POWER SUPPLIES, BYPASSING, AND GROUNDING
All precision converter products require careful application of
good grounding practices to maintain full rated performance.
Because the AD5626 has been designed for 5 V applications, it
is ideal for those applications under microprocessor or micro-
computer control. In these applications, digital noise is prevalent;
therefore, special care must be taken to ensure that its inherent
precision is maintained by exercising particularly good engineering
judgment when addressing the power supply, grounding, and
bypassing issues using the AD5626.
Use a well-filtered and regulated power supply for the AD5626.
The device has been completely characterized for a 5 V supply
with a tolerance of ±5%. Because a 5 V logic supply is almost
universally available, it is not recommended to connect the
DAC directly to an unfiltered logic supply without careful
filtering. Tapping a logic circuit supply for the DAC supply
is unwise because fast logic with nanosecond transition edges
induce high current pulses. The high transient current pulses
can generate glitches hundreds of millivolts in amplitude due
to wiring resistances and inductances. This high frequency
noise corrupts the analog circuits internal to the DAC and
causes errors.
Even though their spike noise is lower in amplitude, directly
tapping the output of a 5 V system supply can cause errors
because these supplies are of the switching regulator type that
can and do generate a great deal of high frequency noise. There-
fore, power the DAC and any associated analog circuitry directly
from the system power supply outputs using appropriate filtering.
Figure 25 illustrates how a clean, analog-grade supply can be
generated from a 5 V logic supply using a differential LC filter
with separate power supply and return lines. With the values
shown, this filter can easily handle 100 mA of load current
without saturating the ferrite cores. Higher current capacity
can be achieved with larger ferrite cores. For lowest noise, all
electrolytic capacitors should be of the low equivalent series
resistance (ESR) type.
06
75
7-
0
25
FERRITE BEADS:
2 TURNS
+5V
RETURN
TTL/CMOS
LOGIC
CIRCUITS
5V
POWER SUPPLY
100F
ELECT.
10-20F
TANT.
0.1F
CER.
+
Figure 25. Properly Filtering a 5 V Logic Supply Yields a High Quality
Analog Supply
To fit the AD5626 in an 8-lead package, only one ground
connection to the device is accommodated. The ground
connection of the DAC serves as the return path for supply
currents as well as the reference point for the digital input
thresholds. The ground connection also serves as the supply rail
for the internal voltage reference and the output amplifier.
Therefore, to minimize errors, connect the ground connection
of the AD5626 to a high quality analog ground, such as the one
previously described. Generous bypassing of the DACs supply
effectively reduces supply line induced errors. Local supply
bypassing consisting of a 10 μF tantalum electrolytic capacitor
in parallel with a 0.1 μF ceramic capacitor is recommended.
Connect the decoupling capacitors between the DAC supply
pin (Pin 1) and the analog ground (Pin 7).
Figure 26 shows how the ground and bypass connections
should be made to the AD5626.
06
75
7-
02
6
CS
CLR
SCLK
LDAC
SDIN
2
8
6
5
3
4
VOUT
1
7
VDD
5V
GND
AD5626
+
10F
0.1F
TO ANALOG GROUND
Figure 26. Recommended Grounding and Bypassing Scheme for the AD5626
UNIPOLAR OUTPUT OPERATION
This is the basic mode of operation for the AD5626. As shown
in Figure 27, the AD5626 is designed to drive loads as low as
2 kΩ in parallel with 500 pF. The code table for this operation is
provided in Table 6.
06
75
7-
02
7
CS
CLR
SCLK
LDAC
SDIN
2
8
6
5
3
4
VOUT
1
7
VDD
GND
AD5626
10F
2k
500pF
0.1F
5V
+
0V ≤ VOUT ≤ 4.095V
Figure 27. Unipolar Output Operation
Table 6. Unipolar Code Table
Hexadecimal Number
in DAC Register
Decimal Number
in DAC Register
Analog Output
Voltage (V)
FFF
4095
4.095
801
2049
2.049
800
2048
2.048
7FF
2047
2.047
000
0
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