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參數(shù)資料
| 型號： | AD5626BRMZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC NANO 12BIT 8-MSOP |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 50 |
| 系列： | nanoDAC™ |
| 設(shè)置時間： | 16µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 12.5mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應商設(shè)備封裝： | 8-MSOP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | * |
AD5626
Rev. A | Page 6 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
0
67
57
-0
03
VDD 1
CS 2
SCLK 3
SDIN 4
VOUT
8
GND
7
CLR
6
LDAC
5
AD5626
TOP VIEW
(Not to Scale)
0
67
57
-0
04
VDD 1
SCLK 3
SDIN 4
VOUT
8
GND
7
AD5626
TOP VIEW
(Not to Scale)
CS 2
CLR
6
LDAC
5
Figure 3. 8-Lead MSOP Pin Configuration
Figure 4. 8-Lead LFCSP Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
VDD
Positive Supply. Nominal value 5 V ± 5%.
2
CS
Chip Select. Active low input.
3
SCLK
Clock Input. Clock input for the internal serial input shift register.
4
SDIN
Serial Data Input. Data on this pin is clocked into the internal serial register on positive clock edges of the
SCLK pin. The most significant bit (MSB) is loaded first.
5
LDAC
Serial Register Data Write to DAC Register. Active low input that writes the serial register data into the DAC
register. Asynchronous input.
6
CLR
Clear DAC Register. Active low digital input that clears the DAC register to zero, setting the DAC to minimum
scale. Asynchronous input.
7
GND
Ground. Analog ground for the DAC. This also serves as the digital logic ground reference voltage.
8
VOUT
Voltage Output from the DAC. Fixed output voltage range of 0 V to 4.095 V with 1 mV/LSB. An internal
temperature stabilized reference maintains a fixed full-scale voltage independent of time, temperature, and
power supply variations.
Table 5. Control Logic Truth Table1
CLR
Serial Shift Register Function
DAC Register Function
H
X
H
No effect
Latched
L
H
No effect
Latched
L
H
No effect
Latched
L
↑+
H
Shift-register-data advanced one bit
Latched
↑+
L
H
Shift-register-data advanced one bit
Latched
H
X
H
↓–
No effect
Updated with current shift register contents
H
X
H
L
No effect
Transparent
H
X
L
X
No effect
Loaded with all zeros
H
X
↑+
H
No effect
Latched all zeros
1
↑+ indicates a positive logic transition; ↓– indicates a negative logic transition; X = don’t care.
2 CS and CLK are interchangeable.
3 Returning CS high avoids an additional false clock of serial data input.
4 Do not clock in serial data while LD is low.
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