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參數(shù)資料
| 型號(hào)： | AD5620ARJ-2500RL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | Single, 12-/14-/16-Bit nanoDAC with 5 ppm/C On-Chip Reference in SOT-23 |
| 中文描述： | SERIAL INPUT LOADING, 8 us SETTLING TIME, 12-BIT DAC, PDSO8 |
| 封裝： | MO-178BA, SOT-23, 8 PIN |
| 文件頁數(shù)： | 20/24頁 |
| 文件大小： | 558K |
| 代理商： | AD5620ARJ-2500RL7 |
AD5620/AD5640/AD5660
AD5660-to-68HC11/68L11 Interface
Figure 46 shows a serial interface between the AD5660 and the
68HC11/68L11 microcontroller. SCK of 68HC11/68L11 drives
the SCLK of AD5660, and the MOSI output drives the serial
data line of the DAC. The SYNC signal is derived from a port line
(PC7). The set-up conditions for correct operation of this
interface are as follows: The 68HC11/68L11 should be con-
figured so that its CPOL bit is 0, and its CPHA bit is 1. When
data is being transmitted to the DAC, the SYNC line is taken
low (PC7). When the 68HC11/68L11 is configured in this way,
data appearing on the MOSI output is valid on the falling edge
of SCK. Serial data from the 68HC11/68L11 is transmitted in
8-bit bytes with only eight falling clock edges occurring in the
transmit cycle. Data is transmitted MSB first. To load data to the
AD5660, PC7 is left low after the first eight bits are transferred, a
second serial write operation is performed to the DAC, and PC7
is taken high at the end of this procedure.
Rev. A | Page 20 of 24
AD5660
1
1
ADDITIONAL PINS OMITTED FOR CLARITY
PC7
SCK
MOSI
SYNC
SCLK
DIN
0
68HC11/68L11
1
Figure 46. AD5660-to-68HC11/68L11 Interface
AD5660-to-80C51/80L51 Interface
Figure 47 shows a serial interface between the AD5660 and the
80C51/80L51 microcontroller. The setup for the interface is as
follows: TxD of the 80C51/80L51 drives SCLK of the AD5660,
and RxD drives the serial data line of the part. The SYNC signal
is again derived from a bit-programmable pin on the port. In
this case, Port Line P3.3 is used. When data is to be transmitted
to the AD5660, P3.3 is taken low. The 80C51/80L51 transmit
data only in 8-bit bytes; therefore, only eight falling clock edges
occur in the transmit cycle. To load data to the DAC, P3.3 is left
low after the first eight bits are transmitted, and a second write
cycle is initiated to transmit the second byte of data. P3.3 is taken
high following the completion of this cycle. The 80C51/80L51
output the serial data LSB first; however, the AD5660 requires
its data with the MSB as the first bit received. The 80C51/80L51
transmit routine should take this into account.
80C51/80L51
1
AD5660
1
P3.3
TxD
RxD
SYNC
SCLK
DIN
0
1
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 47. AD5660-to-80C51/80L51 Interface
AD5660-to-MICROWIRE Interface
Figure 48 shows an interface between the AD5660 and any
MICROWIRE-compatible device. Serial data is shifted out on
the falling edge of the serial clock and is clocked into the
AD5660 on the rising edge of the SK.
MICROWIRE
1
AD5660
1
CS
SK
SO
SYNC
SCLK
DIN
0
1
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 48. AD5660-to-MICROWIRE Interface
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