參數(shù)資料
型號(hào): AD5620
廠商: Analog Devices, Inc.
元件分類: 串行DAC
英文描述: Single, 12-/14-/16-Bit nanoDAC with 5 ppm/C On-Chip Reference in SOT-23
中文描述: 單,12-/14-/16-Bit 5分之/ C對(duì)芯片參考采用SOT - 23 nanoDAC系列
文件頁(yè)數(shù): 7/24頁(yè)
文件大?。?/td> 558K
代理商: AD5620
AD5620/AD5640/AD5660
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2. See Figure 2.
V
DD
= 2.7 V to 5.5 V; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
Limit at T
MIN
, T
MAX
Parameter
V
DD
= 2.7 V to 3.6 V
V
DD
= 3.6 V to 5.5 V
t
11
50
33
t
2
13
13
t
3
13
13
t
4
13
13
t
5
5
5
t
6
4.5
4.5
t
7
0
0
t
8
50
33
t
9
13
13
t
10
0
0
1
Maximum SCLK frequency is 30 MHz at V
DD
= 3.6 V to 5.5 V and 20 MHz at V
DD
= 2.7 V to 3.6 V.
Rev. A | Page 7 of 24
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge set-up time
Data set-up time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to SCLK fall ignore
SCLK falling edge to SYNC fall ignore
DIN
LSB = DB0
MSB = DB23 FOR AD5660;
MSB = DB15 FOR AD5620/AD5640
SYNC
SCLK
MSB
LSB
t
9
t
10
t
4
t
3
t
2
t
7
t
6
t
5
t
1
t
8
0
Figure 2. Serial Write Operation
相關(guān)PDF資料
PDF描述
AD5620ARJ-1500RL7 Single, 12-/14-/16-Bit nanoDAC with 5 ppm/C On-Chip Reference in SOT-23
AD5620ARJ-1REEL7 Single, 12-/14-/16-Bit nanoDAC with 5 ppm/C On-Chip Reference in SOT-23
AD5640 Single, 12-/14-/16-Bit nanoDAC with 5 ppm/C On-Chip Reference in SOT-23
AD5620BRJ-1REEL7 Single, 12-/14-/16-Bit nanoDAC with 5 ppm/C On-Chip Reference in SOT-23
AD5620BRJ-2500RL7 Single, 12-/14-/16-Bit nanoDAC with 5 ppm/C On-Chip Reference in SOT-23
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