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參數(shù)資料
| 型號： | AD5555CRU-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | Dual, Current-Output, Serial-Input, 16-/14-Bit DAC |
| 中文描述： | SERIAL INPUT LOADING, 0.5 us SETTLING TIME, 14-BIT DAC, PDSO16 |
| 封裝： | MO-153AB, TSSOP-16 |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 1419K |
| 代理商： | AD5555CRU-REEL7 |
AD5545/AD5555
PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
AD5545/
AD5555
TOP VIEW
(Not to Scale)
8
7
6
5
1
4
3
2
9
10
11
12
16
13
14
15
CS
DGND
CLK
V
DD
MSB
LDAC
RS
SDI
V
REF
B
R
FB
B
A
GND
B
I
OUT
B
R
FB
A
A
GND
A
I
OUT
A
V
REF
A
02918-0-002
Figure 2. 16-Lead TSSOP
Table 3. Pin Function Descriptions—16-Lead TSSOP
Pin No.
Mnemonic
1
R
FB
A
2
V
REF
A
Function
Establish voltage output for DAC A by connecting to external amplifier output.
DAC A Reference Voltage Input Terminal. Establishes DAC A full-scale output voltage.
Pin can be tied to V
DD
pin.
DAC A Current Output.
DAC A Analog Ground.
DAC B Analog Ground.
DAC B Current Output.
DAC B Reference Voltage Input Terminal. Establishes DAC B full-scale output voltage.
Pin can be tied to V
DD
pin.
Establish voltage output for DAC B by connecting to external amplifier output.
Serial Data Input. Input data loads directly into the shift register.
RESET Pin, Active Low Input. Input registers and DAC registers are set to all 0s or
midscale. Register Data = 0x0000 when MSB = 0. Register Data = 0x8000 for AD5545 and
0x2000 for AD5555 when MSB = 1.
Chip Select, Active Low Input. Disables shift register loading when high. Transfers serial
register data to the input register when CS/LDAC returns high. This does not affect LDAC
operation.
Digital Ground Pin.
Positive Power Supply Input. Specified range of operation 5 V ± 10% or 3 V ± 10%.
MSB bit sets output to either 0 or midscale during a RESET pulse (RS) or at system power-
on. Output equals zero scale when MSB = 0 and midscale when MSB = 1. MSB pin can
also be tied permanently to ground or V
DD
.
Load DAC Register Strobe, Level Sensitive Active Low. Transfers all input register data to
DAC registers. Asynchronous active low input. See Table 4 and Table 5 for operation.
Clock Input. Positive edge clocks data into shift register.
3
4
5
6
7
I
OUT
A
A
GND
A
A
GND
B
I
OUT
B
V
REF
B
8
9
10
R
FB
B
SDI
RS
11
CS
12
13
14
DGND
V
DD
MSB
15
LDAC
16
CLK
Rev. 0 | Page 6 of 16
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