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參數(shù)資料
| 型號： | AD5555CRU-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | Dual, Current-Output, Serial-Input, 16-/14-Bit DAC |
| 中文描述： | SERIAL INPUT LOADING, 0.5 us SETTLING TIME, 14-BIT DAC, PDSO16 |
| 封裝： | MO-153AB, TSSOP-16 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 1419K |
| 代理商： | AD5555CRU-REEL7 |
AD5545/AD5555
CIRCUIT OPERATION
The AD5545/AD5555 contain a 16-/14-bit, current-output,
digital-to-analog converter, a serial-input register, and a DAC
register. Both parts require a minimum of a 3-wire serial data
interface with additional LDAC for dual channel simultaneous
update.
Rev. 0 | Page 11 of 16
D/A CONVERTER SECTION
The DAC architecture uses a current-steering R-2R ladder
design. Figure 16 shows the typical equivalent DAC. The DAC
contains a matching feedback resistor for use with an external
I-to-V converter amplifier. The R
FB
pin is connected to the
output of the external amplifier. The I
OUT
terminal is connected
to the inverting input of the external amplifier. These DACs are
designed to operate with both negative or positive reference
voltages. The V
DD
power pin is used only by the logic to drive
the DAC switches ON and OFF. Note that a matching switch is
used in series with the internal 5 k feedback resistor. If users
attempt to measure the R
FB
value, power must be applied to V
DD
to achieve continuity. The
V
REF
input voltage and the digital data
(
D
) loaded into the corresponding DAC register, according to
Equation 1 and Equation 2, determine the DAC output voltage.
536
,
65
/
–
D
V
V
REF
OUT
×
=
(1)
384
,
16
/
–
D
V
V
REF
OUT
×
=
(2)
Note that the output full-scale polarity is the opposite of the
V
REF
polarity for dc reference voltages.
V
REF
DIGITAL INTERFACE CONNECTIONS OMITTED FOR CLARITY:
SWITCHES S1 AND S2 ARE CLOSED, V
DD
MUST BE POWERED
R
2R
2R
2R
R
5k
S2
S1
R
R
V
DD
R
FB
I
OUT
GND
02918-0-005
Figure 16. Equivalent R-2R DAC Circuit
These DACs are also designed to accommodate ac reference
input signals. The AD5545/AD5555 will accommodate input
reference voltages in the range of –12 V to +12 V. The reference
voltage inputs exhibit a constant nominal input-resistance value
of 5 k, ±30%. The DAC output (I
OUT
) is code dependent,
producing various output resistances and capacitances. When
choosing an external amplifier, the user should take into
account the variation in impedance generated by the
AD5545/AD5555 on the amplifiers inverting input node. The
feedback resistance in parallel with the DAC ladder resistance
dominates output voltage noise.
V
REF
A
DIGITAL INTERFACE CONNECTIONS OMITTED FOR CLARITY:
SWITCHES S1 AND S2 ARE CLOSED, V
DD
MUST BE POWERED
R
2R
2R
2R
R
5k
S2
S1
+3V
–3V
R
R
V
OUT
V
IN
V
DD
5V
2.500V
R
FB
A
I
OUT
A
A
GND
A
GND
02918-0-006
AD5545/AD5555
ADR03
AD8628
LOAD
V
OUT
V
EE
V
CC
Figure 17. Recommended System Connections
SERIAL DATA INTERFACE
The AD5545/AD5555 use a minimum 3-wire (CS, SDI, CLK)
serial data interface for single channel update operation. With
Table 4 as an example (AD5545), users can tie LDAC low and
RS high, then pull CS low for an 18-bit duration. New serial data
is then clocked into the serial-input register in an 18-bit data-
word format with the MSB bit loaded first. Table 5 defines the
truth table for the AD5555. Data is placed on the SDI pin and
clocked into the register on the positive clock edge of CLK. For
the AD5545, only the last 18-bits clocked into the serial register
will be interrogated when the CS pin is strobed high, transfer-
ring the serial register data to the DAC register and updating
the output. If the applied microcontroller outputs serial data in
different lengths than the AD5545, such as 8-bit bytes, three
right justified data bytes can be written to the AD5545. The
AD5545 will ignore the six MSB and recognize the 18 LSB as
valid data. After loading the serial register, the rising edge of
CS transfers the serial register data to the DAC register and
updates the output; during the CS strobe, the CLK should not
be toggled.
If users want to program each channel separately but update
them simultaneously, they need to program LDAC and RS high
initially, then pull CS low for an 18-bit duration and program
DAC A with the proper address and data bits. CS is then pulled
high to latch data to the DAC A register. At this time, the output is
not updated. To load DAC B data, pull CS low for an 18-bit dura-
tion and program DAC B with the proper address and data, then
pull CS high to latch data to the DAC B register. Finally, pull
LDAC low and then high to update both the DAC A and DAC B
outputs simultaneously.
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