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參數(shù)資料
| 型號： | AD5554 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Quad, Current-Output Serial-Input, 16-Bit/14-Bit DACs |
| 中文描述： | 四，電流輸出串行輸入，16-Bit/14-Bit數(shù)模轉(zhuǎn)換器 |
| 文件頁數(shù)： | 7/16頁 |
| 文件大?。?/td> | 473K |
| 代理商： | AD5554 |
REV. 0
AD5544/AD5554
–7–
Table II. AD5554 Control-Logic Truth Table
CS
CLK
LDAC
RS
MSB
Serial Shift Register Function
Input Register Function
DAC Register
H
L
L
L
↑
+
X
L
↑
+
H
L
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
No Effect
No Effect
Shift-Register-Data Advanced One Bit
No Effect
No Effect
Latched
Latched
Latched
Latched
Selected DAC Updated
with Current SR Contents
Latched
Latched
Latched
Latched Data = 0000
H
Latched Data = 2000
H
Latched
Latched
Latched
Latched
Latched
H
H
H
H
H
X
X
X
X
X
L
H
↑
+
H
H
H
H
H
L
L
X
X
X
0
H
No Effect
No Effect
No Effect
No Effect
No Effect
Transparent
Latched
Latched
Latched Data = 0000
H
Latched Data = 2000
H
NOTES
1. SR = Shift Register.
2.
↑
+ positive logic transition; X = Don’t Care.
3. At power ON both the Input Register and the DAC Register are loaded with all zeros.
4. For AD5544, data appears at the SDO Pin 19 clock pulses after input at the SDI pin.
5. For AD5554, data appears at the SDO Pin 17 clock pulses after input at the SDI pin.
Table III. AD5544 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format
MSB
LSB
Bit Position B17
B16
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1 B0
Data Word A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1 D0
NOTE
Only the last 18 bits of data clocked into the serial register (Address + Data) are inspected when the
CS
line’s positive edge returns to logic high. At this point an inter-
nally generated load strobe transfers the serial register data contents (Bits D15–D0) to the decoded DAC-Input-Register address determined by bits A1 and A0. Any
extra bits clocked into the AD5544 shift register are ignored, only the last 18 bits clocked in are used. If double-buffered data is not needed, the
LDAC
pin can be tied
logic low to disable the DAC Registers.
Table IV. AD5554 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format
MSB
LSB
Bit Position B15
Data Word
B14
A0
B13
D13
B12
D12
B11
D11
B10
D10
B9
D9
B8
D8
B7
D7
B6
D6
B5
D5
B4
D4
B3
D3
B2
D2
B1
D1
B0
D0
A1
NOTE
Only the last 16 bits of data clocked into the serial register (Address + Data) are inspected when the
CS
line’s positive edge returns to logic high. At this point an inter-
nally generated load strobe transfers the serial register data contents (Bits D13–D0) to the decoded DAC-Input-Register address determined by bits A1 and A0. Any
extra bits clocked into the AD5554 shift register are ignored, only the last 16 bits clocked in are used. If double-buffered data is not needed, the
LDAC
pin can be tied
logic low to disable the DAC Registers.
Table V. Address Decode
A1
A0
DAC Decoded
0
0
1
1
0
1
0
1
DAC A
DAC B
DAC C
DAC D
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