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參數(shù)資料
| 型號： | AD5554 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Quad, Current-Output Serial-Input, 16-Bit/14-Bit DACs |
| 中文描述： | 四，電流輸出串行輸入，16-Bit/14-Bit數(shù)模轉(zhuǎn)換器 |
| 文件頁數(shù)： | 15/16頁 |
| 文件大?。?/td> | 473K |
| 代理商： | AD5554 |
REV. 0
AD5544/AD5554
–15–
EN
SHIFT REGISTER
ADDRESS
DECODER
A
B
C
D
TO INPUT REGISTER
19
TH
/17
TH
CLOCK
SDO
SDI
CLK
CS
Figure 9. AD5544/AD5554 Equivalent Logic Interface
POWER-ON RESET
When the V
DD
power supply is turned ON, an internal reset
strobe forces all the Input and DAC registers to the zero-code
state or half-scale, depending on the MSB pin voltage. The V
DD
power supply should have a smooth positive ramp without
drooping in order to have consistent results, especially in the
region of V
DD
= 1.5 V to 2.3 V. The V
SS
supply has no effect on
the power-ON reset performance. The DAC register data will
stay at zero or half-scale setting until a valid serial register data
load takes place.
ESD Protection Circuits
All logic-input pins contain back-biased ESD protection Zeners
connected to ground (DGND) and V
DD
as shown in Figure 9.
V
DD
DIGITAL
INPUTS
5k
DGND
Figure 10. Equivalent ESD Protection Circuits
PCB LAYOUT
In PCB layout, all analog ground, A
GND
X, should be tied together.
Ampli
fi
ers suitable for I-to-V conversion include:
High Accuracy: OP97, OP297
Speed and Accuracy: OP42
±
5 V Applications: OP162/OP262/OP462, OP184/OP284/
OP484
APPLICATIONS
The AD5544/AD5554 are inherently 2-quadrant multiplying
D/A converters. That is, they can be easily set up for unipolar
output operation. The full-scale output polarity is the inverse of
the reference-input voltage.
In some applications it may be necessary to generate the full 4-
quadrant multiplying capability or a bipolar output swing. This
is easily accomplished using an additional external ampli
fi
er
(A2) con
fi
gured as a summing ampli
fi
er (see Figure 11). In this
circuit the
fi
rst and second ampli
fi
ers (A1 and A2) provide a
total gain-of-2 which increases the output voltage span to 20V.
Biasing the external ampli
fi
er with a 10 V offset from the refer-
ence voltage results in a full 4-quadrant multiplying circuit. The
transfer equation of this circuit shows that both negative and
positive output voltages are created as the input data (D) is
incremented from code zero (V
OUT
=
–
10 V) to midscale (V
OUT
= 0 V) to full-scale (V
OUT
= 10 V).
V
D
V
OUT
REF
=
×
32768
1
(For AD5544)
(Equation 3)
V
D
V
OUT
REF
=
×
8192
1
(For AD5554)
(Equation 4)
A2
A1
ONE CHANNEL
AD5544
I
OUT
X
R
FB
X
V
REF
X
V
DD
V
SS
A
GND
F
A
GND
X
V
OUT
10k
10k
5k
AD588
V
REF
10V
DIGITAL INTERFACE CONNECTIONS
OMITTED FOR CLARITY.
–
10V < V
OUT
< +10V
Figure 11. Four-Quadrant Multiplying Application Circuit
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參數(shù)描述 |
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