參數(shù)資料
型號(hào)： AD5551BR
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： 5 V, Serial-Input Voltage-Output, 14-Bit DACs
中文描述： SERIAL INPUT LOADING, 1 us SETTLING TIME, 14-BIT DAC, PDSO8
封裝： MS-012AA, NSOIC-8
文件頁(yè)數(shù)： 9/12頁(yè)
文件大?。?/td> 208K
代理商： AD5551BR
AD5551/AD5552
–9–
REV. 0
The AD5552 has an
LDAC
function that allows the DAC latch
to be updated asynchronously by bringing
LDAC
low after
CS
goes high.
LDAC
should be maintained high while data is written
to the shift register. Alternatively,
LDAC
may be tied permanently
low to update the DAC synchronously. With
LDAC
tied perma-
nently low, the rising edge of
CS
will load the data to the DAC.
Unipolar Output Operation
These DACs are capable of driving unbuffered loads of 60 k
.
Unbuffered operation results in low-supply current, typically
300
μ
A, and a low-offset error. The AD5551 provides a unipolar
output swing ranging from 0 V to V
REF
. The AD5552 can be
configured to output both unipolar and bipolar voltages. Fig-
ure 3 shows a typical unipolar output voltage circuit. The code
table for this mode of operation is shown in Table I.
AD5551/AD5552
AD820/
OP196
DGND
*
AD5552 ONLY
V
DD
CS
V
REFS
*
V
REFF
*
OUT
SCLK
LDAC
*
DIN
AGND
5V
2.5V
EXTERNAL
OP AMP
UNIPOLAR
OUTPUT
10 F
0.1 F
0.1 F
SERIAL
INTERFACE
Figure 3. Unipolar Output
Table I. Unipolar Code Table
DAC Latch Contents
MSB
11 1111 1111 1111
10 0000 0000 0000
00 0000 0000 0001
00 0000 0000 0000
LSB
Analog Output
V
REF
×
(16383/16384)
V
REF
×
(8192/16384) = 1/2 V
REF
V
REF
×
(1/16384)
0 V
Assuming a perfect reference, the worst-case output voltage may
be calculated from the following equation.
Unipolar Mode Worst-Case Output
V
D
2
14
V
(
V
V
INL
OUT UNI
REF
GE
ZSE
–
)
=
×
+
+
+
where
V
OUT–UNI
= Unipolar Mode Worst-Case Output
D
= Decimal Code Loaded to DAC
V
REF
= Reference Voltage Applied to Part
V
GE
= Gain Error in Volts
V
ZSE
= Zero Scale Error in Volts
INL
= Integral Nonlinearity in Volts
Bipolar Output Operation
With the aid of an external op amp, the AD5552 may be config-
ured to provide a bipolar voltage output. A typical circuit of
such operation is shown in Figure 4. The matched bipolar offset
resistors R
FB
and R
INV
are connected to an external op amp to
achieve this bipolar output swing where R
FB
= R
INV
= 28 k
.
Table II shows the transfer function for this output operating
mode. Also provided on the AD5552 are a set of Kelvin connec-
tions to the analog ground inputs.
AD5551/AD5552
DGND
V
DD
CS
V
REFS
V
REFF
OUT
SCLK
LDAC
DIN
5V
2.5V
EXTERNAL
OP AMP
BIPOLAR
OUTPUT
10 F
SERIAL
INTERFACE
0.1 F
0.1 F
INV
R
INV
+5V
–
5V
R
FB
RFB
AGNDS
AGNDF
Figure 4. Bipolar Output (AD5552 Only)
Table II. Bipolar Code Table
DAC Latch Contents
MSB
11 1111 1111 1111
10 0000 0000 0000
00 0000 0000 0001
00 0000 0000 0000
00 0000 0000 0000
LSB
Analog Output
+V
REF
×
(8191/8192)
+V
REF
×
(1/8192)
0 V
–V
REF
×
(1/8192)
–V
REF
×
(8191/8192) = –V
REF
Assuming a perfect reference, the worst-case bipolar output
voltage may be calculated from the following equation.
Bipolar Mode Worst-Case Output
(
1
V
V
V
RD
V
RD
RD A
OUT BIP
OUT UNI
–
OS
REF
–
–
/
=
+
)
(
+
(
)
+
(
)
[
]
+
+
2
1
2
where
V
OS
= External Op Amp Input Offset Voltage
RD
= R
FB
and R
IN
Resistor Matching Error, Unitless
A
= Op Amp Open-Loop Gain
Output Amplifier Selection
For bipolar mode, a precision amplifier should be used, supplied
from a dual power supply. This will provide the
±
V
REF
output.
In a single-supply application, selection of a suitable op amp
may be more difficult as the output swing of the amplifier does
not usually include the negative rail, in this case AGND. This
can result in some degradation of the specified performance
unless the application does not use codes near zero.
The selected op amp needs to have very low-offset voltage, (the
DAC LSB is 152
μ
V with a 2.5 V reference), to eliminate the
need for output offset trims. Input bias current should also be
very low as the bias current multiplied by the DAC output
impedance (approximately 6K) will add to the zero code error.
Rail-to-rail input and output performance is required. For fast
settling, the slew rate of the op amp should not impede the
settling time of the DAC. Output impedance of the DAC is
constant and code-independent, but in order to minimize gain
errors, the input impedance of the output amplifier should be
as high as possible. The amplifier should also have a 3 dB band-
width of 1 MHz or greater. The amplifier adds another time
constant to the system, hence increasing the settling time of the
output. A higher 3 dB amplifier bandwidth results in a faster
effective settling time of the combined DAC and amplifier.
相關(guān)PDF資料
PDF描述
AD5552 5 V, Serial-Input Voltage-Output, 14-Bit DACs
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