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參數(shù)資料
| 型號： | AD5551BR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 5 V, Serial-Input Voltage-Output, 14-Bit DACs |
| 中文描述： | SERIAL INPUT LOADING, 1 us SETTLING TIME, 14-BIT DAC, PDSO8 |
| 封裝： | MS-012AA, NSOIC-8 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 208K |
| 代理商： | AD5551BR |
AD5551/AD5552
–8–
REV. 0
100
90
0%
10
CLOCK (5V/DIV)
V
OUT
(50mV/DIV)
2 s/DIV
V
REF
= 2.5V
V
DD
= 5V
T
A
= 25 C
TPC 13. Digital Feedthrough
100
90
0%
10
2μs/DIV
V
REF
= 2.5V
V
DD
= 5V
T
A
= 25 C
CS
(5V/DIV)
V
OUT
(0.1V/DIV)
TPC 14. Digital-to-Analog Glitch Impulse
GENERAL DESCRIPTION
The AD5551/AD5552 are single, 14-bit, serial input, voltage
output DACs. They operate from a single supply ranging from
2.7 V to 5 V and consume typically 300 A with a supply of
5 V. Data is written to these devices in a 14-bit word format, via
a 3- or 4-wire serial interface. To ensure a known power-up state,
these parts were designed with a power-on reset function. In uni-
polar mode, the output is reset to 0 V, while in bipolar mode, the
AD5552 output is set to –V
REF
. Kelvin sense connections for
the reference and analog ground are included on the AD5552.
Digital-to-Analog Section
The DAC architecture consists of two matched DAC sections.
A simplified circuit diagram is shown in Figure 2. The DAC
architecture of the AD5551/AD5552 is segmented. The four
MSBs of the 14-bit data word are decoded to drive 15 switches,
E1 to E15. Each of these switches connects one of 15 matched
resistors to either AGND or V
REF
. The remaining 10 bits of the
data word drive switches S0 to S9 of a 10-bit voltage mode
R-2R ladder network.
R
V
OUT
2R
2R
2R
R
2R
2R
2R
2R
S0
S1
S9
E1
E2
E15
V
REF
10-BIT R-2R LADDER
FOUR MSBs DECODED INTO
15 EQUAL SEGMENTS
Figure 2. DAC Architecture
100
90
0%
10
V
REF
= 2.5V
V
DD
= 5V
T
A
= 25 C
10pF
50pF
200pF
100pF
2μs/DIV
CS
(5V/DIV)
V
OUT
(0.5V/DIV)
TPC 15. Large Signal Settling Time
V
OUT
(1V/DIV)
V
(50mV/DIV)
GAIN =
–
216
100
90
0%
10
V
REF
= 2.5V
V
DD
= 5V
T
A
= 25 C
0.5 s/DIV
TPC 16. Small Signal Settling Time
With this type of DAC configuration, the output impedance
is independent of code, while the input impedance seen by the ref-
erence is heavily code dependent. The output voltage is dependent
on the reference voltage as shown in the following equation.
V
V
D
OUT
REF
N
=
×
2
where
D
is the decimal data word loaded to the DAC register
and
N
is the resolution of the DAC. For a reference of 2.5 V,
the equation simplifies to the following.
V
D
OUT
=
×
2 5
16 384
,
.
giving a
V
OUT
of 1.25 V with midscale loaded, and 2.5 V with
full-scale loaded to the DAC.
The LSB size is V
REF
/16,384.
Serial Interface
The AD5551 and AD5552 are controlled by a versatile 3-wire
serial interface, which operates at clock rates up to 25 MHz and
is compatible with SPI, QSPI, MICROWIRE, and DSP interface
standards. The timing diagram can be seen in Figure 1. Input
data is framed by the chip select input,
CS
. After a high-to-low
transition on
CS
, data is shifted synchronously and latched into
the input register on the rising edge of the serial clock, SCLK.
Data is loaded MSB first in 14-bit words. After 14 data bits
have been loaded into the serial input register, a low-to-high
transition on
CS
transfers the contents of the shift register to the
DAC. Data can only be loaded to the part while
CS
is low.
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