參數(shù)資料
型號： AD5541AARMZ-REEL7
廠商： Analog Devices Inc
文件頁數(shù)： 8/20頁
文件大小： 0K
描述： IC DAC 16BIT SERIAL IN 10MSOP
標(biāo)準(zhǔn)包裝： 1,000
系列： nanoDAC™
設(shè)置時(shí)間： 1µs
位數(shù)： 16
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 單電源
功率耗散（最大）： 825µW
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 10-TFSOP，10-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 10-MSOP
包裝： 帶卷 (TR)
輸出數(shù)目和類型： *
采樣率（每秒）： 1M
AD5541A
Rev. A | Page 16 of 20
FORCE SENSE AMPLIFIER SELECTION
Use single-supply, low noise amplifiers. A low output impedance at
high frequencies is preferred because the amplifiers must be
able to handle dynamic currents of up to ±20 mA.
REFERENCE AND GROUND
Because the input impedance is code dependent, drive the refer-
ence pin from a low impedance source. The AD5541A operates
with a voltage reference ranging from 2 V to VDD. References
below 2 V result in reduced accuracy. The full-scale output
voltage of the DAC is determined by the reference. Table 8
outlines the analog output voltage or particular digital codes.
If the application does not require separate force and sense
lines, tie the lines close to the package to minimize voltage
drops between the package leads and the internal die.
POWER-ON RESET
The AD5541A has a power-on reset function to ensure that the
output is at a known state on power-up. On power-up, the DAC
register contains all 0s until the data is loaded from the serial
register. However, the serial register is not cleared on power-up;
therefore, its contents are undefined. When loading data initially
to the DAC, 16 bits or more should be loaded to prevent erroneous
data appearing on the output. If more than 16 bits are loaded,
the last 16 are kept, and if less than 16 bits are loaded, bits remain
from the previous word. If the AD5541A must be interfaced
with data shorter than 16 bits, pad the data with 0s at the LSBs.
POWER SUPPLY AND REFERENCE BYPASSING
For accurate high resolution performance, it is recommended
that the reference and supply pins be bypassed with a 10 μF
tantalum capacitor in parallel with a 0.1 μF ceramic capacitor.
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