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參數(shù)資料
| 型號： | AD5449YRUZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 29/29頁 |
| 文件大小： | 0K |
| 描述： | IC DAC DUAL 12BIT MULT 16TSSOP |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 1,000 |
| 設(shè)置時間： | 80ns |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 3.5µW |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電流，單極；4 電流，雙極 |
| 采樣率（每秒）： | 2.47M |
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AD5429/AD5439/AD5449
Data Sheet
Rev. E | Page 8 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
NC = NO CONNECT
16
15
14
13
12
11
10
9
IOUT2A
RFBA
VREFA
SCLK
LDAC
GND
IOUT1A
IOUT2B
RFBB
VREFB
SYNC
SDIN
SDO
CLR
VDD
IOUT1B
AD5429/
AD5439/
AD5449
TOP VIEW
(Not to Scale)
04464-005
Figure 6. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
IOUT1A
DAC A Current Output.
2
IOUT2A
DAC A Analog Ground. This pin should typically be tied to the analog ground of the system, but it can be
biased to achieve single-supply operation.
3
RFBA
DAC Feedback Resistor Pin. This pin establishes voltage output for the DAC by connecting to an external
amplifier output.
4
VREFA
DAC A Reference Voltage Input Pin.
5
GND
Ground Pin.
6
LDAC
Load DAC Input. This pin allows asynchronous or synchronous updates to the DAC output. The DAC is
asynchronously updated when this signal goes low. Alternatively, if this line is held permanently low, an
automatic or synchronous update mode is selected, whereby the DAC is updated on the 16th clock falling
edge when the device is in standalone mode, or on the rising edge of SYNC when in daisy-chain mode.
7
SCLK
Serial Clock Input. By default, data is clocked into the input shift register on the falling edge of the serial clock
input. Alternatively, by means of the serial control bits, the device can be configured such that data is clocked
into the shift register on the rising edge of SCLK.
8
SDIN
Serial Data Input. Data is clocked into the 16-bit input register on the active edge of the serial clock input. By
default, data is clocked at power-on into the shift register on the falling edge of SCLK. The control bits allow
the user to change the active edge to a rising edge.
9
SDO
Serial Data Output. This pin allows a number of parts to be daisy-chained. By default, data is clocked into the
shift register on the falling edge and clocked out via SDO on the rising edge of SCLK. Data is always clocked
out on the alternate edge to loading data to the shift register. Writing the readback control word to the shift
register makes the DAC register contents available for readback on the SDO pin, and they are clocked out on the
next 16 opposite clock edges to the active clock edge.
10
SYNC
Active Low Control Input. This pin provides the frame synchronization signal for the input data. When SYNC
goes low, it powers on the SCLK and DIN buffers, and the input shift register is enabled. Data is loaded into the
shift register on the active edge of the subsequent clocks. In standalone mode, the serial interface counts the
clocks, and data is latched into the shift register on the 16th active clock edge.
11
CLR
Active Low Control Input. This pin clears the DAC output, input, and DAC registers. Configuration mode allows the
user to enable the hardware CLR pin as a clear-to-zero scale or midscale, as required.
12
VDD
Positive Power Supply Input. These parts can be operated from a supply of 2.5 V to 5.5 V.
13
VREFB
DAC B Reference Voltage Input Pin.
14
RFBB
DAC B Feedback Resistor Pin. This pin establishes voltage output for the DAC by connecting to an external
amplifier output.
15
IOUT2B
DAC B Analog Ground. This pin typically should be tied to the analog ground of the system, but it can be
biased to achieve single-supply operation.
16
IOUT1B
DAC B Current Output.
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