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參數(shù)資料
| 型號： | AD5432YRM-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 10BIT MULTIPLYING 10-MSOP |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 設計資源： | Unipolar, Precision DC Digital-to-Analog Conversion Using AD5426/32/43 8-Bit to12-Bit DACs (CN0034) Precision, Bipolar Configuration for the AD5426/32/43 8-Bit to12-Bit DACs (CN0036) AC Signal Processing Using AD5426/32/43 Current Output DACs (CN0037) Programmable Gain Element Using AD5426/32/43 Current Output DACs (CN0038) |
| 標準包裝： | 1,000 |
| 位數(shù)： | 10 |
| 數(shù)據(jù)接口： | 串行 |
| 轉換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應商設備封裝： | 10-MSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電流，單極；2 電流，雙極 |
| 采樣率（每秒）： | 2.5M |
Data Sheet
AD5426/AD5432/AD5443
Rev. G | Page 15 of 24
THEORY OF OPERATION
current output DACs consisting of a standard inverting R-2R
ladder configuration. A simplified diagram for the 8-bit AD5426 is
value of R. The value of R is typically 10 kΩ (minimum 8 kΩ
and maximum 12 kΩ). If IOUT1 and IOUT2 are kept at the same
potential, a constant current flows in each ladder leg, regardless
of digital input code. Therefore, the input resistance presented
at VREF is always constant and nominally of value R. The DAC
output (IOUT) is code-dependent, producing various resistances
and capacitances. External amplifier choice should take into
account the variation in impedance generated by the DAC on
the amplifiers inverting input node.
VREF
IOUT2
DAC DATA LATCHES
AND DRIVERS
IOUT1
RFBA
2R
S1
2R
S2
2R
S3
2R
S8
R
03162-041
Figure 40. Simplified Ladder
Access is provided to the VREF, RFB, IOUT1, and IOUT2 terminals of
the DAC, making the device extremely versatile and allowing it
to be configured in several different operating modes. For example,
it can be configured to provide a unipolar output, 4-quadrant
multiplication in bipolar or single-supply modes of operation.
Note that a matching switch is used in series with the internal
RFB feedback resistor. If users attempt to measure RFB, power
must be applied to VDD to achieve continuity.
CIRCUIT OPERATION
Unipolar Mode
Using a single op amp, these devices can easily be configured to
provide 2-quadrant multiplying operation or a unipolar output
voltage swing, as shown in Figure 41.
When an output amplifier is connected in unipolar mode, the
output voltage is given by
n
REF
OUT
D
V
2
where D is the fractional representation of the digital word
loaded to the DAC, and n is the number of bits.
D
= 0 to 255 (8-bit AD5426)
= 0 to 1023 (10-bit AD5432)
= 0 to 4095 (12-bit AD5443)
Note that the output voltage polarity is opposite to the VREF
polarity for dc reference voltages.
These DACs are designed to operate with either negative or
positive reference voltages. The VDD power pin is used by only the
internal digital logic to drive the DAC switches’ on and off states.
These DACs are also designed to accommodate ac reference
input signals in the range of 10 V to +10 V.
With a fixed 10 V reference, the circuit shown in Figure 41 gives
a unipolar 0 V to 10 V output voltage swing. When VIN is an ac
signal, the circuit performs 2-quadrant multiplication. Table 5
shows the relationship between digital code and expected output
voltage for unipolar operation (AD5426, 8-bit device).
Table 5. Unipolar Code Table
Digital Input
Analog Output (V)
1111 1111
VREF (255/256)
1000 0000
VREF (128/256) = VREF/2
0000 0001
VREF (1/256)
0000 0000
VREF (0/256) = 0
VOUT = 0
TO –VREF
SCLK SDIN GND
VREF
SYNC
IOUT2
IOUT1
RFB
AGND
AD5426/
AD5432/
AD5443
R1
R2
A1
VREF
VDD
C1
NOTES
1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
MICROCONTROLLER
03162-042
A1
Figure 41. Unipolar Operation
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