參數(shù)資料
型號(hào): AD5432YRM-REEL7
廠商: Analog Devices Inc
文件頁(yè)數(shù): 15/25頁(yè)
文件大?。?/td> 0K
描述: IC DAC 10BIT MULTIPLYING 10-MSOP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
產(chǎn)品變化通告: Product Discontinuance 27/Oct/2011
設(shè)計(jì)資源: Unipolar, Precision DC Digital-to-Analog Conversion Using AD5426/32/43 8-Bit to12-Bit DACs (CN0034)
Precision, Bipolar Configuration for the AD5426/32/43 8-Bit to12-Bit DACs (CN0036)
AC Signal Processing Using AD5426/32/43 Current Output DACs (CN0037)
Programmable Gain Element Using AD5426/32/43 Current Output DACs (CN0038)
標(biāo)準(zhǔn)包裝: 1,000
位數(shù): 10
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 單電源
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-MSOP
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 2 電流,單極;2 電流,雙極
采樣率(每秒): 2.5M
Data Sheet
AD5426/AD5432/AD5443
Rev. G | Page 21 of 24
Standalone Mode
After power-on, write 1001 to the control word to disable daisy-
chain mode. The first falling edge of SYNC resets a counter that
counts the number of serial clocks, ensuring the correct number
of bits are shifted in and out of the serial shift registers. A rising
edge on SYNC during a write causes the write cycle to be aborted.
After the falling edge of the 16th SCLK pulse, data is auto-
matically transferred from the input shift register to the DAC.
For another serial transfer to take place, the counter must be
reset by the falling edge of SYNC.
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