參數(shù)資料
型號(hào)： AD5432BRM
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： 8-/10-/12-Bit High Bandwidth Multiplying DACs with Serial Interface
中文描述： SERIAL INPUT LOADING, 0.035 us SETTLING TIME, 10-BIT DAC, PDSO10
封裝： 3 X 5 MM, MICRO, SOIC-10
文件頁(yè)數(shù)： 21/32頁(yè)
文件大?。?/td> 860K
代理商： AD5432BRM
AD5429/AD5439/AD5449
SYNC Function
Rev. 0 | Page 21 of 32
SYNC is an edge-triggered input that acts as a frame synchron-
ization signal and chip enable. Data can be transferred into the
device only while SYNC is low. To start the serial data transfer,
SYNC should be taken low, observing the minimum SYNC
falling to SCLK falling edge setup time, t
4
.
Daisy-Chain Mode
Daisy-chain mode is the default power-on mode. To disable the
daisy-chain function, write 1001 to the control word. In daisy-
chain mode, the internal gating on SCLK is disabled. The SCLK
is continuously applied to the input shift register when SYNC is
low. If more than 16 clock pulses are applied, the data ripples
out of the shift register and appears on the SDO line. This data
is clocked out on the rising edge of SCLK (this is the default, use
the control word to change the active edge) and is valid for the
next device on the falling edge (default). By connecting this line
to the SDIN input on the next device in the chain, a multidevice
interface is constructed. For each device in the system, 16 clock
pulses are required. Therefore, the total number of clock cycles
must equal 16
,
where
N
is the total number of devices in the
chain. See Figure 3.
When the serial transfer to all devices is complete, SYNC should
be taken high. This prevents additional data from being clocked
into the input shift register. A burst clock containing the exact
number of clock cycles can be used and SYNC taken high some
time later. After the rising edge of SYNC, data is automatically
transferred from each device’s input shift register to the
addressed DAC. When control bits = 0000, the device is in no
operation mode. This might be useful in daisy-chain applica-
tions, in which the user does not wish to change the settings of a
particular DAC in the chain. Write 0000 to the control bits for
that DAC, and the following data bits are ignored.
Standalone Mode
After power-on, write 1001 to the control word to disable daisy-
chain mode. The first falling edge of SYNC resets a counter that
counts the number of serial clocks to ensure that the correct
number of bits are shifted in and out of the serial shift registers.
A SYNC edge during the 16-bit write cycle causes the device to
abort the current write cycle.
After the falling edge of the 16th SCLK pulse, data is automat-
ically transferred from the input shift register to the DAC. In
order for another serial transfer to take place, the counter must
be reset by the falling edge of SYNC.
LDAC Function
The LDAC function allows asynchronous or synchronous
updates to the DAC output. The DAC is asynchronously
updated when this signal goes low. Alternatively, if this line is
held permanently low, an automatic or synchronous update
mode is selected, whereby the DAC is updated on the 16th clock
falling edge when the device is in standalone mode, or on the
rising edge of SYNC when in daisy-chain mode.
Table 11. DAC Control Bits
C3
C2
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
C1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
C0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DAC
A and B
A
A
A
B
B
B
A and B
A and B
-
-
-
-
-
-
-
Function Implemented
No operation (power-on default)
Load and update
Initiate readback
Load input register
Load and update
Initiate readback
Load input register
Update DAC outputs
Load input registers
Daisy chain disable
Clock data to shift register on rising edge
Clear DAC output to zero scale
Clear DAC output to midscale
Control word
Reserved
No operation
CONTROL BITS
1
1
0
1
SDO2 SDO1
DSY
HCLR SCLK
X
X
X
X
X
X
X
DB0 (LSB)
DB15 (MSB)
0
Figure 46. Control Register Loading Sequence
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