參數(shù)資料
型號(hào)： AD5432BRM
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： 8-/10-/12-Bit High Bandwidth Multiplying DACs with Serial Interface
中文描述： SERIAL INPUT LOADING, 0.035 us SETTLING TIME, 10-BIT DAC, PDSO10
封裝： 3 X 5 MM, MICRO, SOIC-10
文件頁(yè)數(shù)： 15/32頁(yè)
文件大?。?/td> 860K
代理商： AD5432BRM
AD5429/AD5439/AD5449
GENERAL DESCRIPTION
The AD5429/AD5439/AD5449 are 8-, 10-, and 12-bit dual-
channel current output DACs consisting of a standard inverting
R2R ladder configuration. A simplified diagram of one DAC
channel for the AD5449 is shown in Figure 36. The feedback
resistor R
FB
has a value of R. The value of R is typically 10 k
(minimum 8 k and maximum 12 k). If I
OUT
1 and I
OUT
2 are
kept at the same potential, a constant current flows in each
ladder leg, regardless of digital input code. Therefore, the input
resistance presented at V
REF
is always constant.
Rev. 0 | Page 15 of 32
2R
S1
2R
S2
2R
S3
2R
S12
2R
DAC DATA LATCHES
AND DRIVERS
2R
R
FB
A
I
OUT
1A
I
OUT
2A
V
REF
A
0
R
R
R
Figure 36. Simplified Ladder
Access is provided to the V
REF
, R
FB
, I
OUT
1, and I
OUT
2 terminals of
the DACs, making the devices extremely versatile and allowing
them to be configured in several operating modes, such as
unipolar mode, bipolar output mode, or single-supply mode.
UNIPOLAR MODE
Using a single op amp, these devices can easily be configured to
provide 2-quadrant multiplying operation or a unipolar output
voltage swing, as shown in Figure 37.
When an output amplifier is connected in unipolar mode, the
output voltage is given by
n
REF
OUT
V
D
V
2
×
=
where D is the fractional representation of the digital word
loaded to the DAC, and n is the number of bits.
D
= 0 to 255 (AD5429)
= 0 to 1023 (AD5439)
= 0 to 4095 (AD5449)
With a fixed 10 V reference, the circuit shown in Figure 37 gives
a unipolar 0 V to 10 V output voltage swing. When V
IN
is an ac
signal, the circuit performs 2-quadrant multiplication.
Table 5 shows the relationship between digital code and the
expected output voltage for unipolar operation for the AD5429.
Table 5. Unipolar Code Table
Digital Input
Analog Output (V)
1111 1111
V
REF
(4095/4096)
1000 0000
V
REF
(2048/4096) = V
REF
/2
0000 0001
V
REF
(1/4096)
0000 0000
V
REF
(0/4096) = 0
AD5429/
AD5439/
AD5449
SDIN
SCLK
0
NOTES:
1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
3. DAC B OMITTED FOR CLARITY.
I
OUT
1A
I
OUT
2A
GND
V
REF
V
DD
C1
A1
V
OUT
= 0V TO –V
REF
AGND
R2
V
DD
V
REF
SYNC
μ
CONTROLLER
R
FB
A
R1
Figure 37. Unipolar Operation
相關(guān)PDF資料
PDF描述
AD5432YRM 8-/10-/12-Bit High Bandwidth Multiplying DACs with Serial Interface
AD5432YRM-REEL 8-/10-/12-Bit High Bandwidth Multiplying DACs with Serial Interface
AD5432YRM-REEL7 8-/10-/12-Bit High Bandwidth Multiplying DACs with Serial Interface
AD5440 Dual 8-,10-,12-Bit High Bandwidth Multiplying DACs with Serial Interface
AD5443 Dual 8-,10-,12-Bit High Bandwidth Multiplying DACs with Serial Interface
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