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參數(shù)資料
| 型號(hào)： | AD5425YRM-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 9/25頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 8BIT MULTIPLYING 10-MSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 設(shè)置時(shí)間： | 15ns |
| 位數(shù)： | 8 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 25µW |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電流，單極；2 電流，雙極 |
| 采樣率（每秒）： | 9.5M |
| 配用： | EVAL-AD5425EBZ-ND - BOARD EVALUATION FOR AD5425 |
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AD5425
Data Sheet
Rev. C | Page 16 of 24
SINGLE-SUPPLY APPLICATIONS
Current Mode Operation
is biased positive by an amount applied to VBIAS. In this config-
uration, the output voltage is given by
VOUT = [D × (RFB/RDAC) × (VBIAS VIN)] + VBIAS
As D varies from 0 to 255, the output voltage varies from
VOUT = VBIAS to VOUT = 2VBIAS VIN
Figure 32. Single-Supply Current Mode Operation
VBIAS should be a low impedance source capable of sinking and
sourcing all possible variations in current at the IOUT2 terminal
without any problems.
It is important to note that VIN is limited to low voltages because
the switches in the DAC ladder no longer have the same source-
drain drive voltage. As a result, their on resistance differs and
this degrades the linearity of the DAC.
Voltage Switching Mode of Operation
Figure 33 shows this DAC operating in the voltage switching
mode. The reference voltage VIN is applied to the IOUT1 pin,
IOUT2 is connected to AGND, and the output voltage is available
at the VREF terminal. In this configuration, a positive reference
voltage results in a positive output voltage, making single-
supply operation possible. The output from the DAC is voltage
at a constant impedance (the DAC ladder resistance), thus an
op amp is necessary to buffer the output voltage. The reference
input no longer sees constant input impedance, but one that
varies with code. So, the voltage input should be driven from a
low impedance source.
Figure 33. Single-Supply Voltage Switching Mode Operation
It is important to note that VIN is limited to low voltage because
the switches in the DAC ladder no longer have the same source
drain drive voltage. As a result, their on resistance differs, which
degrades the linearity of the DAC.
VIN must also not go negative by more than 0.3 V, otherwise an
internal diode turns on, exceeding the maximum ratings of the
device. In this type of application, the full range of the DAC
multiplying capability is lost.
POSITIVE OUTPUT VOLTAGE
Note that the output voltage polarity is opposite to the VREF
polarity for dc reference voltages. To achieve a positive voltage
output, an applied negative reference to the input of the DAC
is preferred over the output inversion through an inverting
amplifier because of the resistor tolerance errors. To generate
a negative reference, the reference can be level shifted by an
op amp such that the VOUT and GND pins of the reference
become the virtual ground and 2.5 V respectively, as shown
Figure 34. Positive Voltage Output with Minimum of Components
VOUT
GND
VIN
IOUT2
IOUT1
RFB
A1
VREF
VDD
VBIAS
VDD
C1
NOTES:
1. ADDITIONAL PINS OMITTED FOR CLARITY.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE
REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER.
A1
03161-032
VIN
R2
R1
VOUT
GND
IOUT2
IOUT1
RFB
A1
VREF
VDD
NOTES:
1. ADDITIONAL PINS OMITTED FOR CLARITY.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
A1
03161-033
NOTES:
1. ADDITIONAL PINS OMITTED FOR CLARITY.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1 IS A
HIGH SPEED AMPLIFIER.
VOUT = 0V
TO +2.5V
GND
IOUT2
IOUT1
RFB
A1
VREF
VDD = 5V
VDD
C1
GND
VIN
VOUT
ADR03
–2.5V
–5V
+5V
03161-
034
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