Figure 10. Linearity vs. VBIAS Voltage Applied " />
參數(shù)資料
型號(hào): AD5425YRM-REEL7
廠商: Analog Devices Inc
文件頁數(shù): 2/25頁
文件大?。?/td> 0K
描述: IC DAC 8BIT MULTIPLYING 10-MSOP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 1,000
設(shè)置時(shí)間: 15ns
位數(shù): 8
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 單電源
功率耗散(最大): 25µW
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-MSOP
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 2 電流,單極;2 電流,雙極
采樣率(每秒): 9.5M
配用: EVAL-AD5425EBZ-ND - BOARD EVALUATION FOR AD5425
Data Sheet
AD5425
Rev. C | Page 9 of 24
Figure 10. Linearity vs. VBIAS Voltage Applied to IOUT2
Figure 11. Gain and Offset Errors vs. VBIAS Voltage Applied to IOUT2
Figure 12. Linearity vs. VBIAS Voltage Applied to IOUT2
Figure 13. Gain and Offset Errors vs. Voltage Applied to IOUT2
Figure 14. Gain and Offset Errors vs. VBIAS Voltage Applied to IOUT2
Figure 15. Linearity vs. VBIAS Voltage Applied to IOUT2
03161-010
VBIAS (V)
1.5
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
LSBs
0.5
0.3
0.1
–0.1
–0.3
–0.5
MAX INL
MIN INL
MAX DNL
MIN DNL
TA = 25°C
VDD = 3V
VREF = 0V
03161-011
VBIAS (V)
1.5
0.5
1.0
VOLTAGE
(mV)
1.4
0.8
1.0
1.2
0.4
0.6
0
0.2
–0.2
–0.4
GAIN ERROR
OFFSET ERROR
TA = 25°C
VDD = 3V
VREF = 0V
03161-012
VBIAS (V)
2.5
0.5
1.0
1.5
2.0
LSBs
0.5
0.3
–0.1
0.1
–0.3
–0.5
MAX INL
MIN INL
MAX DNL
MIN DNL
VDD = 5V
VREF = 0V
03161-013
VBIAS (V)
2.5
0.5
1.0
1.5
2.0
VOLTAGE
(mV)
2.5
2.0
1.5
1.0
0.5
0
–0.5
GAIN ERROR
OFFSET ERROR
VDD = 5V
VREF = 0V
03161-014
VBIAS (V)
2.5
0
0.5
1.0
1.5
2.0
VOLTAGE
(mV)
10.0
6.0
8.0
2.0
4.0
–2.0
0
–4.0
GAIN ERROR
OFFSET ERROR
TA = 25°C
VDD = 5V
VREF = 2.5V
03161-015
VBIAS (V)
2.0
0
0.5
1.0
1.5
LSBs
1.0
0.4
0.6
0.8
0
0.2
–0.6
–0.4
–0.2
–0.8
–1.0
MAX INL BIAS
MIN INL BIAS
TA = 25°C
VDD = 5V
VREF = 2.5V
MAX DNL BIAS
MIN DNL BIAS
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