參數(shù)資料
型號: AD5425
廠商: Analog Devices, Inc.
英文描述: 8-Bit, High Bandwidth Multiplying DAC with Serial Interface
中文描述: 8位,高帶寬乘法DAC的串行接口
文件頁數(shù): 4/20頁
文件大?。?/td> 417K
代理商: AD5425
REV. 0
–4–
AD5425
TIMING CHARACTERISTICS
1, 2
Parameter
Limit at T
MIN
, T
MAX
50
20
8
8
13
5
3
5
30
0
12
10
Unit
Conditions/Comments
f
SCLK
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Max clock frequency
SCLK cycle time
SCLK high time
SCLK low time
SYNC
falling edge to SCLK falling edge setup time
Data setup time
Data hold time
SYNC
rising edge to SCLK falling edge
Minimum
SYNC
high time
SCLK falling edge to
LDAC
falling edge
LDAC
pulse width
SCLK falling edge to
LDAC
rising edge
NOTES
1
See Figure 1. Temperature range is as follows: Y version: –40
°
C to +125
°
C.
Guaranteed by design and characterization, not subject to production test.
2
All input signals are specified with tr = tf = 1 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
Specifications subject to change without notice.
t
8
SCLK
SYNC
DIN
LDAC
2
LDAC
1
NOTES
1
ASYNCHRONOUS LDAC UPDATE MODE
2
SYNCHRONOUS LDAC UPDATE MODE
DB7
t
4
t
5
t
6
t
2
t
1
t
3
t
7
t
10
t
9
t
11
DB0
Figure 1. Timing Diagram
(V
= 2.5 V to 5.5 V, V
REF
= 10 V, I
OUT
2 = O V. All specifications T
MIN
to T
MAX
, unless
otherwise noted.)
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