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參數資料
| 型號： | AD5425 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 8-Bit, High Bandwidth Multiplying DAC with Serial Interface |
| 中文描述： | 8位，高帶寬乘法DAC的串行接口 |
| 文件頁數： | 15/20頁 |
| 文件大?。?/td> | 417K |
| 代理商： | AD5425 |
REV. 0
AD5425
–15–
MICROPROCESSOR INTERFACING
Microprocessor interfacing to this DAC is via a serial bus that
uses standard protocol compatible with microcontrollers and DSP
processors. The communications channel is a 3-wire interface
consisting of a clock signal, a data signal, and a synchronization
signal. An
LDAC
pin is also included. The AD5425 requires
an 8-bit word with the default being data valid on the falling
edge of SCLK, but this is changeable via the control bits in the
data-word.
ADSP-21xx to AD5425 Interface
The ADSP-21xx family of DSPs are easily interfaced to this family
of DACs without extra glue logic. Figure 11 shows an example
of an SPI interface between the DAC and the ADSP-2191.
SCK of the DSP drives the serial data line, DIN. SYNC is
driven from one of the port lines, in this case SPIxSEL.
SCLK
SCK
AD5425
*
SYNC
SPIxSEL
SDIN
MOSI
ADSP-2191
*
*
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 11. ADSP-2191 SPI to AD5425 Interface
A serial interface between the DAC and DSP SPORT is shown
in Figure 12. In this interface example, SPORT0 is used to
transfer data to the DAC shift register. Transmission is initiated
by writing a word to the Tx register after the SPORT has been
enabled. In a write sequence, data is clocked out on each rising
edge of the DSPs serial clock and clocked into the DAC input
shift register on the falling edge of its SCLK. The update of the
DAC output takes place on the rising edge of the
SYNC
signal.
SCLK
SCLK
AD5425
*
SYNC
TFS
SDIN
DT
ADSP-2101/
ADSP-2103/
ADSP-2191
*
*
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 12. ADSP-2101/ADSP-2103/ADSP-2191 SPORT
to AD5425 Interface
Communication between two devices at a given clock speed is
possible when the following specifications are compatible: frame
sync delay and frame sync setup and hold, data delay and data
setup and hold, and SCLK width. The DAC interface expects a
t
4
(SYNC falling edge to SCLK falling edge setup time) of 13 ns
minimum. Consult the ADSP-21xx User Manual for information
on clock and frame sync frequencies for the SPORT register.
The SPORT Control Register should be set up as follows:
TFSW = 1, Alternate Framing
INVTFS = 1, Active Low Frame Signal
DTYPE = 00, Right Justify Data
ISCLK = 1, Internal Serial Clock
TFSR = 1, Frame Every Word
ITFS = 1, Internal Framing Signal
SLEN = 0111, 8-Bit Data-Word
80C51/80L51 to AD5425 Interface
A serial interface between the DAC and the 8051 is shown in
Figure 13. TxD of the 8051 drives SCLK of the DAC serial
interface, while RxD drives the serial data line, D
IN
. P3.3 is a
bit-programmable pin on the serial port and is used to drive
SYNC
. When data is to be transmitted to the switch, P3.3 is
taken low. The 80C51/80L51 transmits data in 8-bit bytes
which is perfect for the AD5425 as it only requires an 8-bit
word. Data on RxD is clocked out of the microcontroller on
the rising edge of TxD and is valid on the falling edge. As
a
result, no glue logic is required between the DAC and
microcontroller interface. P3.3 is taken high following the
completion of this cycle. The 8051 provides the LSB of its
SBUF register as the first bit in the data stream. The DAC
input register requires its data with the MSB as the first bit
received. The transmit routine should take this into account.
SCLK
TxD
8051
*
SYNC
P1.1
SDIN
RxD
AD5425
*
*
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 13. 80C51/80L51 to AD5425 Interface
MC68HC11 Interface to AD5425 Interface
Figure 14 shows an example of a serial interface between the DAC
and the MC68HC11 microcontroller. The serial peripheral
interface (SPI) on the MC68HC11 is configured for master mode
(MSTR = 1), clock polarity bit (CPOL) = 0, and the clock phase
bit (CPHA) = 1. The SPI is configured by writing to the SPI
control register (SPCR)—see the 68HC11 User Manual
.
SCK
of the 68HC11 drives the SCLK of the DAC interface, the
MOSI output drives the serial data line (D
IN
) of the AD5516. The
SYNC
signal is derived from a port line (PC7). When data is being
transmitted to the AD5516, the
SYNC
line is taken low (PC7).
Data appearing on the MOSI output is valid on the falling edge of
SCK. Serial data from the 68HC11 is transmitted in 8-bit bytes
with only eight falling clock edges occurring in the transmit cycle.
Data is transmitted MSB first. PC7 is taken high at the end of
the write.
SCLK
SCK
AD5425
*
SYNC
PC7
SDIN
MOSI
MC68HC11
*
*
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 14. 68HC11/68L11 to AD5425 Interface
MICROWIRE to AD5425 Interface
Figure 15 shows an interface between the DAC and any
MICROWIRE compatible device. Serial data is shifted out on
the falling edge of the serial clock, SK, and is clocked into the DAC
input shift register on the rising edge of SK, which corresponds
to the falling edge of the DAC’s SCLK.
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