參數(shù)資料
型號: AD5424YCPZ-REEL7
廠商: Analog Devices Inc
文件頁數(shù): 23/29頁
文件大小: 0K
描述: IC DAC 8BIT MULTIPLYING 20-LFCSP
產(chǎn)品培訓模塊: Data Converter Fundamentals
DAC Architectures
標準包裝: 1,500
設置時間: 30ns
位數(shù): 8
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 單電源
功率耗散(最大): 25µW
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 20-VFQFN 裸露焊盤,CSP
供應商設備封裝: 20-LFCSP-VQ
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 2 電流,單極;2 電流,雙極
采樣率(每秒): 20.4M
配用: EVAL-AD5424EBZ-ND - BOARD EVALUATION FOR AD5424
AD5424/AD5433/AD5445
Data Sheet
Rev. D | Page 2 of 28
TABLE OF CONTENTS
REVISION HISTORY
/13—Rev. C to Rev. D
Changes to Figure 4 and Table 4..................................................... 7
Changes to Figure 6 and Table 5..................................................... 8
Changes to Figure 8 and Table 6..................................................... 9
Updated Outline Dimensions....................................................... 25
Changes to Ordering Guide .......................................................... 26
12/12—Rev. B to Rev. C
Changes to General Description Section ...................................... 1
Added Note 2 to Table 1 .................................................................. 4
Added EPAD Note to Table 4 and EPAD Note to Figure 4......... 7
Added EPAD Note to Table 5 and EPAD Note to Figure 6......... 8
Added EPAD Note to Table 6 and EPAD Note to Figure 8......... 9
Deleted the Evaluation Board for AD5424/AD5433/AD5445
Section and Power Supplies for Evaluation Board Section....... 23
Deleted Figure 59; Renumbered Sequentially............................. 24
Deleted Figure 60 and Figure 61................................................... 25
Changes to Ordering Guide .......................................................... 26
Deleted Figure 62 and Table 12; Renumbered Sequentially ..... 26
8/09—Rev. A to Rev. B
Updated Outline Dimensions....................................................... 28
Changes to Ordering Guide.......................................................... 29
3/05—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Changes to Specifications.................................................................4
Changes to Figure 49...................................................................... 17
Changes to Figure 50...................................................................... 18
Changes to Figure 51, Figure 52, and Figure 54......................... 19
Added Microprocessor Interfacing Section................................ 22
Added Figure 59 ............................................................................. 24
Added Figure 60 ............................................................................. 25
10/03—Initial Version: Revision 0
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