參數(shù)資料
型號(hào)： AD5422BCPZ-REEL
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： SERIAL INPUT LOADING, 32 us SETTLING TIME, 16-BIT DAC, QCC40
封裝： 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD-2, LFCSP-40
文件頁數(shù)： 27/40頁
文件大?。?/td> 1323K
代理商： AD5422BCPZ-REEL
AD5412/AD5422
Rev. C | Page 33 of 40
AD5410/AD5420 registers. The update clock frequency for any
given value is the same for all output ranges. The step size,
however, varies across output ranges for a given value of step
size because the LSB size is different for each output range.
Table 24 shows the range of programmable slew times for a full-
scale change on any of the output ranges. The values in Table 24
were obtained using Equation 1.
The digital slew rate control feature results in a staircase
formation on the current output, as shown in Figure 72. This
figure also shows how the staircase can be removed by
connecting capacitors to the CAP1 and CAP2 pins, as described
0
5
10
15
20
25
–10
0
10
20
30
40
50
60
70
80
90
100 110
O
UT
P
UT
CURRE
NT
(
m
A
)
TIME (ms)
TA = 25°C
AVDD = 24V
RLOAD = 300
06
99
6-
1
39
10ms RAMP, SR CLOCK = 0x1, SR STEP = 0x5
50ms RAMP, SR CLOCK = 0xA, SR STEP = 0x7
100ms RAMP, SR CLOCK = 0x8, SR STEP = 0x5
Figure 68. Output Current Slewing Under Control of the Digital Slew Rate
Control Feature
IOUT FILTERING CAPACITORS (LFCSP PACKAGE)
Capacitors can be placed between CAP1 and AVDD, and CAP2
and AVDD, as shown in Figure 69.
CAP1
AVDD
C1
C2
AVDD
AD5412/
AD5422 CAP2
GND
06
99
6-
0
62
IOUT
Figure 69. IOUT Filtering Capacitors
The CAP1 and CAP2 pins are available only on the LFCSP
package. The capacitors form a filter on the current output
circuitry, as shown in Figure 70, reducing the bandwidth and
the slew rate of the output current. Figure 71 shows the effect
the capacitors have on the slew rate of the output current. To
achieve significant reductions in the rate of change, very large
capacitor values are required, which may not be suitable in
some applications. In this case, the digital slew rate control
feature can be used. The capacitors can be used in conjunction
with the digital slew rate control feature as a means of
smoothing out the steps caused by the digital code increments,
as shown in Figure 72.
DAC
IOUT
BOOST
CAP1
CAP2
C1
R1
C2
AVDD
4k
12.5k
40
0
699
6-
06
3
Figure 70. IOUT Filter Circuitry
0
5
–0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
10
15
20
25
O
U
T
P
UT
CU
RRE
NT
(m
A)
TIME (ms)
TA = 25°C
AVDD =24V
RLOAD =300
06
99
6-
142
NO CAPACITOR
10nF ON CAP1
10nF ON CAP2
47nF ON CAP1
47nF ON CAP2
Figure 71. Slew Controlled 4 mA to 20 mA Output Current Step Using
External Capacitors on the CAP1 and CAP2 Pins
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
–1
012
3456
78
O
UT
P
UT
CURRE
NT
(
m
A
)
TIME (ms)
TA = 25°C
AVDD = 24V
RLOAD = 300
NO EXTERNAL CAPS
10nF ON CAP1
10nF ON CAP2
06
99
6-
0
43
Figure 72. Smoothing Out the Steps Caused by the Digital Slew
Rate Control Feature
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