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| 型號： | AD5422BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 31/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 16BIT SRL 40LFCSP |
| 設(shè)計資源： | 16-Bit Fully Isolated Output Module Using AD5422 and ADuM1401 (CN0065) Simplified 16-Bit Voltage Output and 4 mA-to-20 mA Output Solution Using AD5422 (CN0077) |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時間： | 25µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 功率耗散（最大）： | 950mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 40-LFCSP-VQ（6x6） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 輸出數(shù)目和類型： | 1 電流，單極；1 電流，雙極；1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | 40k |
| 其它名稱： | AD5422BCPZ-REEL7DKR |
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Data Sheet
AD5412/AD5422
Rev. I | Page 37 of 44
APPLICATIONS INFORMATION
VOLTAGE AND CURRENT OUTPUT RANGES ON
THE SAME TERMINAL
The current and voltage output pins can be connected together.
A buffer amplifier is required however to prevent a current
leakage path through an internal 40k resistor on the +VSENSE pin,
when the device is in current output mode. In current mode the
VOUT pin is high impedance while in voltage output mode, the
IOUT pin is high impedance and will not affect the voltage
output. It is important that the external RSET be used in this
configuration, as depicted in Figure 77.
IOUT
AD5412/
AD5422
IOUT/VOUT
+VSENSE
–VSENSE
VOUT
RSET
OP07/OP184
06996-
071
Figure 77. IOUT and VOUT Connected Together
DRIVING INDUCTIVE LOADS
When driving inductive or poorly defined loads, connect a
0.01 F capacitor between IOUT and GND. This ensures stability
with loads above 50 mH. There is no maximum capacitance
limit. The capacitive component of the load may cause slower
settling. The digital slew rate control feature may also prove
useful in this situation.
TRANSIENT VOLTAGE PROTECTION
prevent damage from normal handling. The industrial control
environment can, however, subject I/O circuits to much higher
high voltage transients, external power diodes and a surge
current limiting resistor are required, as shown in Figure 78.
The constraint on the resistor value is that, during normal
operation, the output level at IOUT must remain within its voltage
compliance limit of AVDD – 2.5 V, and the two protection diodes
and resistor must have appropriate power ratings. Further
protection can be provided with transient voltage suppressors or
transorbs; these are available as both unidirectional suppressors
(protect against positive high voltage transients) and
bidirectional suppressors (protect against both positive and
negative high voltage transients) and are available in a wide
range of standoff and breakdown voltage ratings. It is
recommended that all field connected nodes be protected.
AVDD
IOUT
RLOAD
RP
AVDD
AD5412/
AD5422
GND
AVSS
06996-
064
Figure 78. Output Transient Voltage Protection
GALVANICALLY ISOLATED INTERFACE
In many process control applications, it is necessary to provide
an isolation barrier between the controller and the unit being
controlled to protect and isolate the controlling circuitry from
any hazardous common-mode voltages that may occur. The
iCoupler products from Analog Devices, Inc., provide voltage
isolation in excess of 2.5 kV. The serial loading structure of the
because the number of interface lines is kept to a minimum.
AD5422 using an ADuM1400. For further information, visit
ENCODE
SERIAL
CLOCK IN
CONTROLLER
ADuM14001
SERIAL
DATA OUT
SYNC OUT
CONTROL
OUT
DECODE
TO
SCLK
TO
SDIN
TO
LATCH
TO
CLEAR
VIA
VOA
ENCODE
DECODE
VIB
VOB
ENCODE
DECODE
VIC
VOC
ENCODE
DECODE
VID
VOD
06996-
065
1ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 79. Isolated Interface
MICROPROCESSOR INTERFACING
bus that uses a protocol compatible with microcontrollers and
DSP processors. The communications channel is a 3-wire
minimum interface consisting of a clock signal, a data signal,
word with data valid on the rising edge of SCLK.
For all interfaces, the DAC output update is initiated on the
rising edge of LATCH. The contents of the registers can be
read using the readback function.
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