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參數(shù)資料
| 型號(hào)： | AD5422BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 27/44頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 16BIT SRL 40LFCSP |
| 設(shè)計(jì)資源： | 16-Bit Fully Isolated Output Module Using AD5422 and ADuM1401 (CN0065) Simplified 16-Bit Voltage Output and 4 mA-to-20 mA Output Solution Using AD5422 (CN0077) |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時(shí)間： | 25µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 功率耗散（最大）： | 950mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 40-LFCSP-VQ（6x6） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 輸出數(shù)目和類型： | 1 電流，單極；1 電流，雙極；1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | 40k |
| 其它名稱： | AD5422BCPZ-REEL7DKR |
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Data Sheet
AD5412/AD5422
Rev. I | Page 33 of 44
AD5412/AD5422 FEATURES
FAULT ALERT
devices to be connected together to one pull-up resistor for
global fault detection. The FAULT pin is forced active by one
of the following fault scenarios:
The voltage at IOUT attempts to rise above the compliance
range, due to an open-loop circuit or insufficient power
supply voltage. The IOUT current is controlled by a PMOS
transistor and internal amplifier, as shown in Figure 66.
The internal circuitry that develops the fault output avoids
using a comparator with window limits because this would
require an actual output error before the FAULT output
becomes active. Instead, the signal is generated when the
internal amplifier in the output stage has less than ~1 V
of remaining drive capability (when the gate of the output
PMOS transistor nearly reaches ground). Thus, the FAULT
output activates slightly before the compliance limit is
reached. Because the comparison is made within the
feedback loop of the output amplifier, the output accuracy
is maintained by its open-loop gain, and an output error
does not occur before the FAULT output becomes active.
approximately 150°C.
The IOUT fault and over temp bits of the status register are used
in conjunction with the FAULT pin to inform the user which
one of the fault conditions caused the FAULT pin to be asserted
(see Table 19 and Table 20).
VOLTAGE OUTPUT SHORT CIRCUIT PROTECTION
Under normal operation, the voltage output sinks/sources
10 mA. The maximum current that the voltage output delivers
is ~20 mA; this is the short-circuit current.
VOLTAGE OUTPUT OVERRANGE
An overrange facility is provided on the voltage output. When
enabled via the control register, the selected output range is
overranged by, typically, 10%.
VOLTAGE OUTPUT FORCE-SENSE
The +VSENSE and VSENSE pins are provided to facilitate remote
sensing of the load connected to the voltage output. If the load
is connected at the end of a long or high impedance cable,
sensing the voltage at the load allows the output amplifier to
compensate and ensure that the correct voltage is applied across
the load. This function is limited only by the available power
supply headroom.
ASYNCHRONOUS CLEAR (CLEAR)
The CLEAR pin is an active high clear that allows the voltage
output to be cleared to either zero-scale code or midscale code,
user selectable via the CLEAR SELECT pin, or the CLRSEL bit
of the control register, as described in Table 21. (The clear select
feature is a logical OR function of the CLEAR SELECT pin and
the CLRSEL bit.) The current output clears to the bottom of its
programmed range. It is necessary for CLEAR to be high for a
minimum amount of time to complete the operation (see Figure 2).
When the CLEAR signal is returned low, the output remains at
the cleared value. The preclear value can be restored by pulsing
the LATCH signal low without clocking any data. A new value
cannot be programmed until the CLEAR pin is returned low.
Table 21. CLRSEL Options
CLRSEL
Output Value
Unipolar Output Range
Bipolar Output Range
0
0 V
1
Midscale
Zero scale
In addition to defining the output value for a clear operation,
the CLRSEL bit and CLEAR SELECT pin also define the default
output value. During selection of a new voltage range, the
output value is as defined in Table 21. To avoid glitches on the
output, it is recommended that, before changing voltage ranges,
the user disable the output by setting the OUTEN bit of the
control register to logic low. When OUTEN is set to logic high,
the output goes to the default value as defined by CLRSEL and
CLEAR SELECT.
INTERNAL REFERENCE
reference with initial accuracy of ±5 mV maximum and a
temperature drift coefficient of ±10 ppm/°C maximum. The
reference voltage is buffered and externally available for use
elsewhere within the system. See Figure 16 for a load regulation
graph of the integrated reference.
EXTERNAL CURRENT SETTING RESISTOR
RSET is an internal sense resistor as part of the voltage-to-current
conversion circuitry (see Figure 66). The stability of the output
current over temperature is dependent on the stability of the
value of RSET. As a method of improving the stability of the
output current over temperature, an external precision 15 kΩ
low drift resistor can be connected to the RSET pin of the
(RSET). The external resistor is selected via the control register
(see Table 14).
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