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參數(shù)資料
| 型號： | AD5405YCPZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC DUAL 12BIT MULT 40LFCSP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 2,500 |
| 設(shè)置時間： | 80ns |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 50µW |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 40-LFCSP-VQ（6x6） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電流，單極；4 電流，雙極 |
| 采樣率（每秒）： | 21.3M |
| 配用： | EVAL-AD5405EB-ND - BOARD EVAL FOR AD5405 |
AD5405
Rev. B | Page 15 of 24
Table 6 shows the relationship between the digital code and the
expected output voltage for bipolar operation.
Table 6. Bipolar Code
Digital Input
Analog Output (V)
1111 1111 1111
+VREF (4,095/4,096)
1000 0000 0000
0
0000 0000 0001
VREF (4,095/4,096)
0000 0000 0000
VREF (4,096/4,096)
Stability
In the I-to-V configuration, the IOUT of the DAC and the
inverting node of the op amp must be connected as close as
possible, and proper PCB layout techniques must be used.
Because every code change corresponds to a step function, gain
peaking may occur if the op amp has limited gain bandwidth
product (GBP) and there is excessive parasitic capacitance at the
inverting node. This parasitic capacitance introduces a pole into
the open-loop response, which can cause ringing or instability
in the closed-loop applications circuit.
An optional compensation capacitor, C1, can be added in parallel
small a value of C1 can produce ringing at the output, whereas
too large a value can adversely affect the settling time. C1 should
be found empirically, but 1 pF to 2 pF is generally adequate for
the compensation.
SINGLE-SUPPLY APPLICATIONS
Voltage-Switching Mode of Operation
Figure 34 shows the DAC operating in the voltage-switching
mode. The reference voltage, VIN, is applied to the IOUT1A pin,
IOUT2A is connected to AGND, and the output voltage is
available at the VREFA terminal. In this configuration, a positive
reference voltage results in a positive output voltage, making
single-supply operation possible. The output from the DAC is
voltage at a constant impedance (the DAC ladder resistance).
Therefore, an op amp is necessary to buffer the output voltage.
The reference input no longer sees a constant input impedance,
but one that varies with code. Therefore, the voltage input
should be driven from a low impedance source.
VOUT
VDD
GND
VIN
IOUT2A
IOUT1A
RFBA VDD
VREFA
R2
R1
04463-009
NOTES
1. SIMILAR CONFIGURATION FOR DAC B.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 34. Single-Supply Voltage-Switching Mode
Note that VIN is limited to low voltages because the switches in the
DAC ladder no longer have the same source-drain drive voltage.
As a result, their on resistance differs and degrades the integral
linearity of the DAC. Also, VIN must not go negative by more
than 0.3 V, or an internal diode turns on, causing the device to
exceed the maximum ratings. In this type of application, the full
range of multiplying capability of the DAC is lost.
Positive Output Voltage
The output voltage polarity is opposite to the VREF polarity for
dc reference voltages. To achieve a positive voltage output, an
applied negative reference to the input of the DAC is preferred
over the output inversion through an inverting amplifier because
of the resistor’s tolerance errors. To generate a negative reference,
the reference can be level-shifted by an op amp such that the
VOUT and GND pins of the reference become the virtual ground
and 2.5 V, respectively, as shown in Figure 35.
VOUT = 0V TO +2.5V
VDD = +5V
GND
IOUT2A
IOUT1A
RFBA
VDD
VREFA
C1
GND
VIN
VOUT
ADR03
+5V
–5V
12-BIT DAC
–2.5V
04463-010
NOTES
1. SIMILAR CONFIGURATION FOR DAC B.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 35. Positive Voltage Output with Minimum Components
ADDING GAIN
In applications where the output voltage must be greater than
VIN, gain can be added with an additional external amplifier, or
it can be achieved in a single stage. Consider the effect of temper-
ature coefficients of the thin film resistors of the DAC. Simply
placing a resistor in series with the RFB resistor causes mismatches
in the temperature coefficients, resulting in larger gain temper-
ature coefficient errors. Instead, the circuit of Figure 36 shows
the recommended method for increasing the gain of the circuit.
R1, R2, and R3 should have similar temperature coefficients,
but they need not match the temperature coefficients of the DAC.
This approach is recommended in circuits where gains of greater
than 1 are required.
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| AD5405YCPZ-REEL7 | 功能描述:IC DAC DUAL 12BIT MULT 40LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:LTC263x 12-, 10-, and 8-Bit VOUT DAC Family 特色產(chǎn)品:LTC2636 - Octal 12-/10-/8-Bit SPI VOUT DACs with 10ppm/°C Reference 標準包裝:91 系列:- 設(shè)置時間:4µs 位數(shù):10 數(shù)據(jù)接口:MICROWIRE?，串行，SPI? 轉(zhuǎn)換器數(shù)目:8 電壓電源:單電源 功率耗散（最大）:2.7mW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:14-WFDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:14-DFN-EP（4x3） 包裝:管件 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
| AD540J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| AD540JH | 制造商:AD84/07 功能描述:Operational Amplifier, Single AMP, Bipolar/JFET, 8 Pin, Metal Can |
| AD540K | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| AD540S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
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