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參數(shù)資料
| 型號： | AD5405YCPZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC DUAL 12BIT MULT 40LFCSP |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 2,500 |
| 設置時間： | 80ns |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 50µW |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 40-LFCSP-VQ（6x6） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電流，單極；4 電流，雙極 |
| 采樣率（每秒）： | 21.3M |
| 配用： | EVAL-AD5405EB-ND - BOARD EVAL FOR AD5405 |
AD5405
Rev. B | Page 18 of 24
PARALLEL INTERFACE
Data is loaded into the AD5405 in a 12-bit parallel word format.
Control lines CS and R/W allow data to be written to or read
from the DAC register. A write event takes place when CS and
R/W are brought low, data available on the data lines fills the
shift register, and the rising edge of CS latches the data and
transfers the latched data-word to the DAC register. The DAC
latches are not transparent; therefore, a write sequence must
consist of a falling and rising edge on CS to ensure that data is
loaded into the DAC register and that its analog equivalent is
reflected on the DAC output. A read event takes place when
R/W is held high and CS is brought low. Data is loaded from the
DAC register, goes back into the input register, and is output
onto the data line, where it can be read back to the controller for
verification or diagnostic purposes. The input and DAC
registers of these devices are not transparent; therefore, a falling
and rising edge of CS is required to load each data-word.
MICROPROCESSOR INTERFACING
ADSP-21xx-to-AD5405 Interface
Figure 38 shows the AD5405 interfaced to the ADSP-21xx
series of DSPs as a memory-mapped device. A single wait state
may be necessary to interface the AD5405 to the ADSP-21xx,
depending on the clock speed of the DSP. The wait state can be
programmed via the data memory wait state control register of
the ADSP-21xx (see the ADSP-21xx family’s user manual for
details).
04463-
049
R/W
DB0 TO DB11
AD54051
ADDRESS
DECODER
CS
DATA 0 TO
DATA 23
ADDRESS BUS
ADDR0 TO
ADRR13
ADSP-21xx1
DATA BUS
DMS
WR
1ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 38. ADSP21xx-to-AD5405 Interface
8xC51-to-AD5405 Interface
Figure 39 shows the interface between the AD5405 and the
8xC51 family of DSPs. To facilitate external data memory
access, the address latch enable (ALE) mode is enabled. The low
byte of the address is latched with this output pulse during
access to the external memory. AD0 to AD7 are the multiplexed
low order addresses and data bus; they require strong internal
pull-ups when emitting 1s. During access to external memory,
A8 to A15 are the high order address bytes. Because these ports
are open drained, they also require strong internal pull-ups
when emitting 1s.
04463-
051
R/W
DB0 TO DB11
AD54051
ADDRESS
DECODER
CS
AD0 TO AD7
ADDRESS BUS
A8 TO A15
80511
DATA BUS
WR
1ADDITIONAL PINS OMITTED FOR CLARITY.
8-BIT
LATCH
ALE
Figure 39. 8xC51-to-AD5405 Interface
ADSP-BF5xx-to-AD5405 Interface
Figure 40 shows a typical interface between the AD5405 and the
ADSP-BF5xx family of DSPs. The asynchronous memory write
cycle of the processor drives the digital inputs of the DAC. The
AMSx line is actually four memory select lines. Internal ADDR
lines are decoded into AMS3–0; these lines are then inserted as
chip selects. The rest of the interface is a standard handshaking
operation.
04463-
050
R/W
DB0 TO DB11
AD54051
ADDRESS
DECODER
CS
DATA 0 TO
DATA 23
ADDRESS BUS
ADDR1 TO
ADRR19
ADSP-BF5xx1
DATA BUS
AMSx
AWE
1ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 40. ADSP-BF5xx-to-AD5405 Interface
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| AD5405YCPZ-REEL7 | 功能描述:IC DAC DUAL 12BIT MULT 40LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓模塊:LTC263x 12-, 10-, and 8-Bit VOUT DAC Family 特色產(chǎn)品:LTC2636 - Octal 12-/10-/8-Bit SPI VOUT DACs with 10ppm/°C Reference 標準包裝:91 系列:- 設置時間:4µs 位數(shù):10 數(shù)據(jù)接口:MICROWIRE?，串行，SPI? 轉(zhuǎn)換器數(shù)目:8 電壓電源:單電源 功率耗散（最大）:2.7mW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:14-WFDFN 裸露焊盤 供應商設備封裝:14-DFN-EP（4x3） 包裝:管件 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
| AD540J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| AD540JH | 制造商:AD84/07 功能描述:Operational Amplifier, Single AMP, Bipolar/JFET, 8 Pin, Metal Can |
| AD540K | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| AD540S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
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