參數(shù)資料
型號： AD5405YCP-REEL7
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： Dual 12-Bit, High Bandwidth, Multiplying DAC with 4-Quadrant Resistors and Parallel Interface
中文描述： PARALLEL, WORD INPUT LOADING, 0.015 us SETTLING TIME, 12-BIT DAC, QCC40
封裝： 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD-2, LFCSP-40
文件頁數(shù)： 3/24頁
文件大?。?/td> 925K
代理商： AD5405YCP-REEL7
AD5405
SPECIFICATIONS
1
V
DD
= 2.5 V to 5.5 V, V
REF
A = V
REF
B = 10 V, I
OUT
2 = 0 V. All specifications T
MIN
to T
MAX,
unless otherwise noted. DC performance measured
with OP1177, AC performance with AD9631, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
STATIC PERFORMANCE
Resolution
12
Relative Accuracy
±1
Differential Nonlinearity
1/+2
Gain Error
±25
Gain Error Temp Coefficient
2
±5
Bipolar Zero-Code Error
±25
Output Leakage Current
±1
±10
REFERENCE INPUT
2
Reference Input Range
±10
V
REF
A, V
REF
B Input Resistance
8
10
12
V
REF
A to V
REF
B Input Resistance
Mismatch
R
1
, R
FB
Resistance
16
20
24
R
2
, R
3
Resistance
16
20
24
R
2
to R
3
Resistance Mismatch
.06
.18
DIGITAL INPUTS/OUTPUT
2
Input High Voltage, V
IH
1.7
Input Low Voltage, V
IL
0.8
0.7
Input Leakage Current, I
IL
1
Input Capacitance
10
V
DD
= 4.5 V to 5.5 V
Output Low Voltage, V
OL
0.4
Output High Voltage, V
OH
V
DD
1
V
DD
= 2.5 V to 3.6 V
Output Low Voltage, V
OL
0.4
Output High Voltage, V
OH
V
DD
0.5
DYNAMIC PERFORMANCE
2
Reference Multiplying BW
10
Output Voltage Settling Time
80
120
Rev. 0 | Page 3 of 24
Unit
Bits
LSB
LSB
mV
ppm FSR/°C
mV
nA
nA
V
k
%
Conditions
Guaranteed monotonic
Data = 0x0000, T
A
= 25°C, I
OUT
1
Data = 0x0000
H
, I
OUT
1
Typical resistor TC =
50 ppm/°C
DAC input resistance
Typ = 25°C, Max = 125°C
1.6
2.5
k
k
%
V
V
V
μA
pF
V
V
V
V
MHz
ns
Typ = 25°C, Max = 125°C
V
DD
= 2.5 V to 5.5 V
V
DD
= 2.7 V to 5.5 V
V
DD
= 2.5 V to 2.7 V
I
SINK
= 200 μA
I
SOURCE
= 200 μA
I
SINK
= 200 μA
I
SOURCE
= 200 μA
V
REF
= 5 V pk-pk, DAC loaded all 1s
Measured to ±1 mV of FS. R
LOAD
= 100 , C
LOAD
=15 pF.
DAC latch alternately loaded with 0s and 1s.
1 LSB change around major carry, V
REF
= 0 V
DAC latch loaded with all 0s. Reference = 10 kHz
DAC latches loaded with all 0s
DAC latches loaded with all 1s
Feedthrough to DAC output with CS high and
alternate loading of all 0s and all 1s
V
REF
= 5 V p-p, all 1s loaded, f = 1 kHz
V
REF
= 5 V, sine wave generated from digital code
@ 1 kHz
Digital Delay
Digital-to-Analog Glitch Impulse
Multiplying Feedthrough Error
Output Capacitance
Digital Feedthrough
20
3
5
40
75
2
4
ns
nV-s
dB
pF
pF
nV-s
Total Harmonic Distortion
Output Noise Spectral Density
75
75
25
dB
dB
nV/√Hz
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