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| 型號： | AD539JNZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/21頁 |
| 文件大小： | 0K |
| 描述： | IC MULT/DIV DUAL CH LIN 16-DIP |
| 標(biāo)準(zhǔn)包裝： | 25 |
| 功能： | 模擬乘法器/除法器 |
| 位元/級數(shù)： | 雙象限 |
| 封裝/外殼： | 16-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 16-PDIP |
| 包裝： | 管件 |
AD539
Rev. B | Page 10 of 20
THEORY OF OPERATION
CIRCUIT DESCRIPTION
Figure 18 shows a simplified schematic of the AD539. Q1 to Q6
are large-geometry transistors designed for low distortion and
low noise. Emitter-area scaling further reduces distortion: Q1 is
three times larger than Q2; Q4 and Q5 are each three times
larger than Q3 and Q6 and are twice as large as Q1 and Q2. A
stable reference current of IREF = 1.375 mA is produced by a
band gap reference circuit and applied to the common emitter
node of a controlled cascode formed by Q1 and Q2. When VX =
0 V, all of IREF flows in Q1 due to the action of the high gain
control amplifier, which lowers the voltage on the base of Q2.
As VX is raised, the fraction of IREF flowing in Q2 is forced to
balance the control current, VX/2.5 kΩ. At the full-scale value of
VX (3 V) this fraction is 0.873. Because the base of Q1, Q4, and
Q5 are at ground potential and the bases of Q2, Q3, and Q6 are
commoned, all three controlled cascodes divide the current
applied to their emitter nodes in the same proportion. The
control loop is stabilized by the external capacitor, CC.
The signal voltages, VY1 and VY2 (generically referred to as VY),
are first converted to currents by voltage-to-current converters
with a gm of 575 μmhos. Thus, the full-scale input of ±2 V
becomes a current of ±1.15 mA, which is superimposed on a
bias of 2.75 mA and applied to the common emitter node of
controlled cascode Q3/Q4 or Q5/Q6. As previously explained,
the proportion of this current steered to the output node is
linearly dependent on VX. Therefore, for full-scale VX and VY
inputs, a signal of ±1 mA (0.873 × ±1.15 mA) and a bias
component of 2.4 mA (0.873 × 2.75 mA) appear at the output.
The bias component absorbed by the 1.25 kΩ resistors also
connected to VX and the resulting signal current can be applied
to an external load resistor (in which case scaling is not
accurate) or can be forced into either or both of the 6 kΩ
feedback resistors (to the Z and W nodes) by an external op
amp. In the latter case, scaling accuracy is guaranteed.
GENERAL RECOMMENDATIONS
The AD539 is a high speed circuit and requires considerable
care to achieve its full performance potential. A high quality
ground plane should be used with the device either soldered
directly into the board or mounted in a low profile socket. In
Figure 18, an open triangle denotes a direct, short connection
to this ground plane; the BASE COMMON pins (Pin 12 and
Pin 13) are especially prone to unwanted signal pickup. Power
supply decoupling capacitors of 0.1 μF to 1 μF should be
connected from the +VS and VS pins (Pin 4 and Pin 5) to the
ground plane. In applications using external high speed op
amps, use separate supply decoupling. It is good practice to
insert small (10 Ω) resistors between the primary supply and
the decoupling capacitor.
The control amplifier compensation capacitor, CC, should
likewise have short leads to ground and a minimum value of
3 nF. Unless maximum control bandwidth is essential, it is
advisable to use a larger value of 0.01 μF to 0.1 μF to improve
the signal channel phase response, high frequency crosstalk,
and high frequency distortion. The control bandwidth is
inversely proportional to this capacitance, typically 2 MHz for CC =
0.01 μF, VX = 1.7 V. The bandwidth and pulse response of the
control channel can be improved by using a feedforward
capacitor of 5% to 20% the value of CC between the VX and
HF COMP pins (Pin 1 and Pin 2). Optimum transient response
results when the rise/fall time of VX are commensurate with the
control channel response time.
VX should not exceed the specified range of 0 V to 3 V. The ac
gain is zero for VX < 0 V but there remains a feedforward path
(see Figure 18) causing control feedthrough. Recovery time
from negative values of VX can be improved by adding a small
signal Schottky diode with its cathode connected to HF COMP
(Pin 2) and its anode grounded. This constrains the voltage
swing on CC. Above VX = 3.2 V, the ac gain limits at its
maximum value, but any overdrive appears as control
feedthrough at the output.
10
15
9
16
14
12
7
13
4
5
1
2
3
6
8
11
BAND-GAP
REFERENCE
GENERATOR
IREF =
1.375mA
1.2mA FS
HF COMP
±1mA FS
+VS
BASE COMMON
VX
0V TO +3V FS
VY1
±2V FS
VY2
±2V FS
CHAN2
OUTPUT
COMMON
CHAN1
OUTPUT
CONTROL
AMPLIFIER
–VS
CC (EXT)
3nF MIN
2.5k
1.25k
INPUT COMMON
1.25k
6k
Q1
Q2
Q3
Q4
Q5
Q6
W2
Z2
W1
Z1
09
67
9
-01
8
Figure 18. Simplified Schematic of AD539 Multiplier (16-Lead SBDIP and PDIP Shown)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD539KD | 制造商:Analog Devices 功能描述:Analog Multiplier/Divider 2-Bit 16-Pin SBCDIP 制造商:Rochester Electronics LLC 功能描述:MULTIPLIER IC - Bulk |
| AD539KDZ | 功能描述:IC MULT/DIV DUAL CH LIN 16-CDIP RoHS:是 類別:集成電路 (IC) >> 線性 - 模擬乘法器，除法器 系列:- 標(biāo)準(zhǔn)包裝:25 系列:HA 功能:模擬乘法器 位元/級數(shù):四象限 封裝/外殼:16-CDIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:16-CDIP 側(cè)面銅焊 包裝:管件 |
| AD539KN | 制造商:Analog Devices 功能描述:Analog Multiplier/Divider 2-Bit 16-Pin PDIP |
| AD539KNZ | 功能描述:IC MULT/DIV DUAL CH LIN 16-DIP RoHS:是 類別:集成電路 (IC) >> 線性 - 模擬乘法器，除法器 系列:- 標(biāo)準(zhǔn)包裝:25 系列:HA 功能:模擬乘法器 位元/級數(shù):四象限 封裝/外殼:16-CDIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:16-CDIP 側(cè)面銅焊 包裝:管件 |
| AD539SD | 制造商:Analog Devices 功能描述:Analog Multiplier/Divider 2-Bit 16-Pin SBCDIP 制造商:Rochester Electronics LLC 功能描述:MULTIPLIER IC - Bulk |
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