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參數(shù)資料
| 型號： | AD5399YRM-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | Twos Complement, Dual 12-Bit DAC with Internal REF and Fast Settling Time |
| 中文描述： | SERIAL INPUT LOADING, 0.8 us SETTLING TIME, 12-BIT DAC, PDSO10 |
| 封裝： | 1.1 MM HEIGHT, MO-187BA, MSOP-10 |
| 文件頁數(shù)： | 11/12頁 |
| 文件大小： | 336K |
| 代理商： | AD5399YRM-REEL7 |
AD5399
Shutdown Function
The AD5399 shutdown function allows both DACs to be
shutdown simultaneously. However, the A0 and SD bits work in
tandem, and the A0 logic state must be the same for shutdown
activation and deactivation (see Table 7).
Rev. D | Page 11 of 12
Table 7. Shutdown Activation and Deactivation Sequence.
Sequence
of Events
in Binary
Shutdown Status
0X10 XXXX
XXXX XXXX
2
1X00 XXXX
XXXX XXXX
3
0X00 XXXX
XXXX XXXX
resume normal operation.
The A0 bit (MSB) must be in the same state when activating and deactivating
shutdown.
Data-Word
Activate shutdown on both DACs.
Both DACs remain at shutdown.
Deactivate shutdown. Both DACs
For users whose logic signals may be in three-state (random
levels) during power-up initialization, it is recommended to put
a pull-up resistor at the CS pin to disable chip select (Figure 24).
This avoids inadvertent shutdown as well as the inability to
deactivate shutdown due to an unknown A0 state. The resistor
value depends on the digital controller’s output impedance.
5V
2V
(D–2048)/4096
×
4V + V
BZ
V
OUTA
V
BZ
(V
REF
)
AGND
DGND
C2
0.1
μ
F
C1
10
μ
F
AD5399
V
TP
V
DD
CS
CLK
SDI
0
R1
300k
Figure 24. Disable CS for Random Logic Mode
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