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參數(shù)資料
| 型號： | AD5399YRM-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | Twos Complement, Dual 12-Bit DAC with Internal REF and Fast Settling Time |
| 中文描述： | SERIAL INPUT LOADING, 0.8 us SETTLING TIME, 12-BIT DAC, PDSO10 |
| 封裝： | 1.1 MM HEIGHT, MO-187BA, MSOP-10 |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 336K |
| 代理商： | AD5399YRM-REEL7 |
AD5399
OPERATION
The AD5399 provides a 12-bit, twos complement, dual voltage
output, digital-to-analog converter (DAC). It has an internal
reference with 2 V bipolar zero dc offset, where 0 ≤ V
OUT
≤ 4 V.
Rev. D | Page 10 of 12
The output transfer equation is
V
OUT
= ((
D
– 2048)/4096 × 4 V) + 2 V
where:
D
is the 12-bit decimal code and not the twos complement code.
V
OUT
is with respect to ground.
In data programming, the data is loaded MSB first on the
positive clock edge (SCLK) after chip select (CS) goes from high
to low. The digital word is 16 bits wide, with the MSB, B15, as an
address bit (DAC A: A0 = 0; DAC B: A0 = 1). B14 is don’t care,
B13 is a shutdown bit, B12 must be logic low, and the last 12 bits
are data bits. An internal counter allows data transferred from
the shift register to the output after the 16
th
positive clock edge
while CS stays low (see Figure 5). After the 16
th
clock pulse, it is
not necessary to bring CS high to shift the data to the output.
However, CS should be brought high anytime after the 16th clock
positive edge in order to allow the next programming cycle.
Table 6. Input Logic Control Truth Table
CLK
CS
Register Activity
L
H
No Shift Register Effect
H
H
No Shift Register Effect
P
L
Shift One SDI Bit into the SR
16
th
P
L
Transfer SR Data into DAC Register and Update
the Output
P = Positive Edge, X = Don't Care, SR = Shift Register.
The data setup and data hold times in the Specifications table
determine the timing requirements. The internal power-on reset
circuit clears the serial input registers to all 0s, and sets the two
DAC registers to a V
BZ
(zero code) of 2 V.
Software shutdown B13 turns off the internal REF and
amplifiers. The output is close to zero potential, and the digital
circuitry remains active such that new data can be written.
Therefore, the DAC register is refreshed with the new data once
the shutdown bit is deactivated.
All digital inputs are ESD protected with a series input resistor
and parallel Zener, as shown in Figure 21, that apply to digital
input pins CLK, SDA, and CS. The basic connection is shown in
Figure 22.
LOGIC
1k
0
Figure 21. Equivalent ESD Protection Circuit
5V
2V
(D–2048)/4096
×
4V + 2V
V
OUTA
V
BZ
(V
REF
)
AGND
DGND
SDI
CLK
V
TP
V
DD
C2
0.1
μ
F
C1
10
μ
F
AD5399
CS
0
Figure 22. Basic Connection
POWER-UP/POWER-DOWN SEQUENCE
Like most CMOS devices, it is recommended to power V
DD
and
ground prior to any digital signals. The ideal power-up
sequence is GND, V
DD
, and digital signals. The reverse sequence
applies to the power-down condition.
Layout and Power Supply Bypassing
It is a good practice to employ compact, minimum lead-length
layout design. The input leads should be as direct as possible
with a minimum conductor length. Ground paths should have
low resistance and low inductance.
Similarly, it is also good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to the
device should be bypassed with 0.01 μF to 0.1 μF disc or chip
ceramic capacitors. Low ESR 1 μF to 10 μF tantalum or electro-
lytic capacitors should also be applied at V
DD
to minimize any
transient disturbance and to filter any low frequency ripple (see
Figure 23). Users should not apply switching regulators for V
DD
due to the power supply rejection ratio degradation over
frequency.
0
AGND
DGND
V
DD
AD5399
C1
0.1
μ
F
C2
10
μ
F
V
DD
+
Figure 23. Power Supply Bypassing and Grounding Connection
Grounding
The DGND and AGND pins of the AD5399 refer to the digital
and analog ground references. To minimize the digital ground
bounce, the DGND terminal should be joined remotely at a
single point to the analog ground plane, as shown in Figure 23.
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