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參數(shù)資料
| 型號(hào)： | AD5399 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 串行DAC |
| 英文描述： | Twos Complement, Dual 12-Bit DAC with Internal REF and Fast Settling Time |
| 中文描述： | 二進(jìn)制補(bǔ)碼，雙12位的內(nèi)部編號(hào)，快速建立時(shí)間援 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大小： | 336K |
| 代理商： | AD5399 |
AD5399
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Rev. D | Page 5 of 12
AD5399
TOP VIEW
(Not to Scale)
CLK
1
SDI
2
DGND
3
V
OUTB
V
OUTA
4
5
CS
V
TP
V
DD
AGND
V
BZ
10
9
8
7
6
0
Figure 3. MSOP-10 Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
1
CLK
2
SDI
3
DGND
4
V
OUTB
5
V
OUTA
6
V
BZ
7
AGND
8
V
DD
9
V
TP
10
CS
Description
Serial Clock Input. Positive edge triggered.
Serial Data Input. MSB first format.
Digital Ground.
DAC B Voltage Output (A0 = Logic 1).
DAC A Voltage Output (A0 = Logic 0).
2 V, Virtual Bipolar Zero (Active Output).
Analog Ground.
Positive Power Supply. Specified for operation at 5 V.
Connect to V
DD
. Reserved for factory testing.
Chip Select (Frame Sync Input). Allows clock and data to shift into the shift register when CS goes from high to low.
After the 16
th
clock pulse, it is not necessary to bring CS high to shift the data to the output. However, CS should be
brought high any time after the 16th clock positive edge in order to allow the next programming cycle.
Table 5. Serial Data-Word Format
ADDR
B15
B14
A0
X
MSB
DATA
B11
D11
B13
SD
B12
0
B10
D10
…
…
B3
D3
B2
D2
B1
D1
B0
D0
LSB
A0
Address Bit. Logic low selects DAC A and logic high selects DAC B.
Both channels are shut down when the SD bit is high. However, the A0 bit must be at the same state for shutdown
activation and deactivation. See the Shutdown Function section.
X
Don’t Care.
SD
Shutdown Bit. Logic high puts both DAC outputs and V
BZ
into high impedance. A0 bit must be at the same state for
shutdown activation and deactivation.
0
B12 must be 0.
D0–D11
Data Bits.
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