參數(shù)資料
型號(hào): AD5399
廠商: Analog Devices, Inc.
元件分類: 串行DAC
英文描述: Twos Complement, Dual 12-Bit DAC with Internal REF and Fast Settling Time
中文描述: 二進(jìn)制補(bǔ)碼,雙12位的內(nèi)部編號(hào),快速建立時(shí)間援
文件頁數(shù): 3/12頁
文件大?。?/td> 336K
代理商: AD5399
AD5399
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
V
DD
= 5 V ± 10%, –40°C < T
A
< +105°C, unless otherwise noted.
Table 2.
Parameter
DC CHARACTERISTICS
Resolution
Differential Nonlinearity Error
Integral Nonlinearity Error
Positive Full-Scale Error
Bipolar Zero-Scale Error
Negative Full-Scale Error
ANALOG OUTPUTS
Nominal Positive Full-Scale
Positive Full-Scale Tempco
2
Nominal V
BZ
Output Voltage
Bipolar Zero Output Resistance
2
V
BZ
Output Voltage Tempco
Nominal Peak-to-Peak Output Swing
DIGITAL INPUTS
Input Logic High
Input Logic Low
Input Current
Input Capacitance
2
POWER SUPPLIES
Power Supply Range
Supply Current
Supply Current in Shutdown
Power Dissipation
3
Power Supply Sensitivity
DYNAMIC CHARACTERISTICS
2
Settling Time
Digital Feedthrough
Bipolar Zero-Scale Glitch
Capacitive Load Driving Capability
INTERFACE TIMING CHARACTERISTICS
2
, 4
SCLK Cycle Frequency
SCLK Clock Cycle Time
Input Clock Pulse Width
Data Setup Time
Data Hold Time
CS to SCLK Active Edge Setup Time
SCLK to CS Hold Time
Repeat Programming, CS High Time
Rev. D | Page 3 of 12
Symbol
N
DNL
INL
V
+FSE
V
BZSE
V
–FSE
V
OUTA/B
TCV
OUTA/B
V
BZ
R
BZ
TCV
BZ
|V
+FS
| + |V
–FS
|
V
IH
V
IL
I
IL
C
IL
V
DD RANGE
I
DD
I
DD_SHDN
P
DISS
P
SS
t
S
Q
G
CL
t
CYC
t
1
t
2
, t
3
t
4
t
5
t
6
t
7
t
8
Conditions
Codes 2048 to 2052, due to int. op amp offset
Code = 0xF
Code = 0x000
Code = 0x800
Code = 0x7FF
Code = 0x7FF, T
A
= 0°C to 70°C
Code = 0xFF, T
A
= –40°C to +105°C
T
A
= 0°C to 70°C
T
A
= –40°C to +105°C
Code 0x7FF to Code 0x800
V
DD
= 5 V
V
DD
= 5 V
V
IN
= 0 V or 5 V, V
DD
= 5 V
V
IH
= V
DD
or V
IL
= 0 V
V
IH
= V
DD
or V
IL
= 0 V, B14 = 0, T
A
= 0°C to 105°C
V
IH
= V
DD
or V
IL
= 0 V, B14 = 0, T
A
= –40°C to 0°C
V
IH
= V
DD
or V
IL
= 0 V, V
DD
= 5.5 V
V
DD
= 5 V ± 10%
0.1% error band
No oscillation
Clock level low or high
Min
12
–1
–1.2
–0.4
–0.75
–0.75
–0.75
–40
–60
1.995
–40
–60
2.4
4.5
–0.006
30
15
5
0
5
0
30
Typ
1
±0.5
±0.5
±0.02
–0.15
–0.15
–0.15
4
±10
±10
2.000
1
±10
±10
4
5
1.8
10
100
9
+0.003
0.8
10
10
Max
+1
+1.2
+0.4
+0.75
+0.75
+0.75
+40
+60
2.004
+40
+60
0.8
±1
5.5
2.6
100
500
13
+0.006
1000
33
Unit
Bits
LSB
LSB
%FS
%FS
%FS
%FS
V
ppm/°C
ppm/°C
V
ppm/°C
ppm/°C
V
V
V
μA
pF
V
mA
μA
μA
mW
%/%
μs
nV-s
nV-s
pF
MHz
ns
ns
ns
ns
ns
ns
ns
1
Typical values represent average readings at 25°C and V
DD
= 5 V.
2
Guaranteed by design and not subject to production test.
3
P
DISS
is calculated from (I
DD
× V
DD
). CMOS logic level inputs result in minimum power dissipation.
4
See timing diagram (Figure 5) for location of measured values. All input control voltages are specified with t
R
= t
F
= 2 ns (10% to 90% of 3 V) and timed from a voltage
level of 1.5 V. Switching characteristics are measured using V
DD
= 5 V. Input logic should have a 1 V/μs minimum slew rate.
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