參數(shù)資料
型號： AD5392BST-5
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： 8-/16-Channel, 3 V/5 V, Serial Input, Single- Supply, 12-/14-Bit Voltage Output DACs
中文描述： SERIAL INPUT LOADING, 8 us SETTLING TIME, 14-BIT DAC, PQFP52
封裝： 10 X 10 MM, MS-026BCC, LQFP-52
文件頁數(shù)： 30/44頁
文件大?。?/td> 1319K
代理商： AD5392BST-5
AD5390/AD5391/AD5392
2-BYTE MODE
The 2-byte mode lets the user update channels sequentially
following initialization of this mode. The device address byte is
required only once and the address pointer is configured for
autoincrement or burst mode.
Rev. A | Page 30 of 44
The user must begin with an address byte (R/W = 0), after
which the DAC acknowledges that it is prepared to receive data
by pulling SDA low. The address byte is followed by a specific
pointer byte (0xFF), which initiates the burst mode of
operation. The address pointer initializes to Channel 0 and the
data following the pointer is loaded to Channel 0. The address
pointer automatically increments to the next address.
The REG0 and REG1 bits in the data byte determine the register
to be updated. In this mode, following the initialization, only the
two data bytes are required to update a channel. The channel
address automatically increments from Address 0 to the final
address and then returns to the normal 3-byte mode of opera-
tion. This mode allows transmission of data to all channels in
one block and reduces the software overhead in configuring all
channels. A STOP condition at any time exits this mode. Toggle
mode of operation is not supported in 2-byte mode. Figure 35
shows a typical configuration.
.
0
REG0
MSB
MSB
LSB
LSB
REG1
1
0
0
A7=1
A6=1
A5=1
A4=1
A3=1
A2=1
A1=1
A0=1
1
1
AD1
AD0
R/W
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SDA
START
CONDITION
BY
MASTER
ACK
BY
CONVERTER
CHANNEL 0 DATA
ACK
BY
CONVERTER
ADDRESS BYTE
POINTER BYTE
CHANNEL 1 DATA
CHANNEL N DATA FOLLOWED BY STOP
MSB
ACK
BY
CONVERTER
ACK
BY
CONVERTER
MOST SIGNIFICANT DATA BYTE
LEAST SIGNIFICANT DATA BYTE
REG0
MSB
MSB
LSB
LSB
REG1
ACK
BY
CONVERTER
ACK
BY
CONVERTER
MOST SIGNIFICANT DATA BYTE
LEAST SIGNIFICANT DATA BYTE
REG0
MSB
MSB
LSB
LSB
REG1
ACK
BY
CONVERTER
ACK
BY
CONVERTER
STOP
CONDITION
BY
MASTER
MOST SIGNIFICANT DATA BYTE
LEAST SIGNIFICANT DATA BYTE
Figure 35. 2-Byte Mode I
2
C Write Operation
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