參數(shù)資料
型號： AD5392BST-5
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： 8-/16-Channel, 3 V/5 V, Serial Input, Single- Supply, 12-/14-Bit Voltage Output DACs
中文描述： SERIAL INPUT LOADING, 8 us SETTLING TIME, 14-BIT DAC, PQFP52
封裝： 10 X 10 MM, MS-026BCC, LQFP-52
文件頁數(shù)： 29/44頁
文件大?。?/td> 1319K
代理商： AD5392BST-5
AD5390/AD5391/AD5392
3-BYTE MODE
The 3-byte mode lets the user update more than one channel in
a write sequence without having to write the device address byte
each time. The device address byte is required only once and
subsequent channel updates require the pointer byte and the
data bytes. In 3-byte mode, the user begins with an address byte
(R/W = 0) after which the DAC acknowledges that it is
prepared to receive data by pulling SDA low. The address byte is
followed by the pointer byte; this addresses the specific channel
in the DAC to be addressed and is also acknowledged by the
DAC. Address Bits A3 to A0 address all channels on the
Rev. A | Page 29 of 44
AD5390/AD5391. Address Bits A2 to A0 address all channels on
the AD5392. Address Bit A3 is a zero on the AD5392. This is
then followed by the two data bytes. REG1 and REG0 determine
the register to be updated.
If a STOP condition is not sent following the data bytes,
another channel can be updated by sending a new pointer
byte followed by the data bytes. This mode requires only three
bytes to be sent to update any channel once the device has
been addressed initially and reduces the software overhead in
updating the AD539x channels. A STOP condition at any time
exits this mode. Figure 34 shows a typical configuration.
0
REG0
MSB
MSB
LSB
LSB
REG1
ACK
BY
CONVERTER
ACK
BY
CONVERTER
STOP
CONDITION
BY
MASTER
REG0
MSB
MSB
LSB
LSB
REG1
1
0
0
0
0
0
0
A3
A2
A1
A0
1
1
AD1
AD0
R/W
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SDA
START
CONDITION
BY
MASTER
ACK
BY
CONVERTER
ACK
BY
CONVERTER
ADDRESS BYTE
POINTER BYTE FOR CHANNEL N
MSB
ACK
BY
CONVERTER
ACK
BY
CONVERTER
ACK
BY
CONVERTER
MOST SIGNIFICANT DATA BYTE
MOST SIGNIFICANT DATA BYTE
POINTER BYTE FOR CHANNEL NEXT CHANNEL
DATA FOR CHANNEL N
DATA FOR CHANNEL NEXT CHANNEL
LEAST SIGNIFICANT DATA BYTE
LEAST SIGNIFICANT DATA BYTE
0
0
0
0
A3
A2
A1
A0
MSB
Figure 34. The 3-Byte Mode I
2
C Write Operation
相關(guān)PDF資料
PDF描述
AD5392BST-5-REEL Quad 12-bit 125MSPS ADC with serialized LVDS output 64-VQFN -40 to 85
AD5390BCP-3 8-/16-Channel, 3 V/5 V, Serial Input, Single- Supply, 12-/14-Bit Voltage Output DACs
AD5391BCP-3 8-/16-Channel, 3 V/5 V, Serial Input, Single- Supply, 12-/14-Bit Voltage Output DACs
AD5392BCP-3 8-/16-Channel, 3 V/5 V, Serial Input, Single- Supply, 12-/14-Bit Voltage Output DACs
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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