參數(shù)資料
型號(hào): AD5392BCP-3
廠商: ANALOG DEVICES INC
元件分類: DAC
英文描述: 8-/16-Channel, 3 V/5 V, Serial Input, Single- Supply, 12-/14-Bit Voltage Output DACs
中文描述: SERIAL INPUT LOADING, 8 us SETTLING TIME, 14-BIT DAC, QCC64
封裝: 9 X 9 MM, MO-220VMMD-4, LFCSP-64
文件頁數(shù): 17/44頁
文件大?。?/td> 1319K
代理商: AD5392BCP-3
AD5390/AD5391/AD5392
Mnemonic
PD
Rev. A | Page 17 of 44
Function
Power-Down (level-sensitive, active high). Used to place the device in low power mode, in which the device consumes
1 μA analog current and 20 μA digital current. In power-down mode, all internal analog circuitry is placed in low power
mode; the analog output is configured as high impedance outputs or provides a 100 k load to ground, depending on
how the power-down mode is configured. The serial interface remains active during power-down.
Interface Select Input Pin. When this input is low, I
2
C mode is selected. When this input is high, SPI mode is selected.
Interface CLOCK Input Pin. In SPI-compatible serial interface mode, this pin acts as a serial clock input. It operates at
clock speeds up to 50 MHz.
I
2
C mode: In I
2
C mode, this pin performs the SCL function, clocking data into the device. Data transfer rate in I
2
C mode is
compatible with both 100 kHz and 400 kHz operating modes.
Interface Data Input Pin.
SPI/I
2
C = 1: This pin acts as the serial data input. Data must be valid on the falling edge of SCLK.
SPI/I
2
C = 0, I
2
C mode: In I
2
C mode, this pin is the serial data pin (SDA) operating as an open drain input/output.
SPI/I
2
C
SCLK/SCL
DIN/SDA
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