參數(shù)資料
型號(hào)： AD5391BST-5-REEL
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： 8-/16-Channel, 3 V/5 V, Serial Input, Single- Supply, 12-/14-Bit Voltage Output DACs
中文描述： SERIAL INPUT LOADING, 6 us SETTLING TIME, 12-BIT DAC, PQFP52
封裝： 10 X 10 MM, MS-026BCC, LQFP-52
文件頁(yè)數(shù)： 24/44頁(yè)
文件大小： 1319K
代理商： AD5391BST-5-REEL
AD5390/AD5391/AD5392
DATA DECODING—AD5390/AD5392
The AD5390/AD5392 contain an internal 14-bit data bus. The
input data is decoded depending on the data loaded to the
REG1 and REG0 bits of the input serial register. This is shown
in Table 10.
Rev. A | Page 24 of 44
Data from the serial input register is loaded into the addressed
DAC input register, offset (c) register, or gain (m) register. The
format data, and the offset (c) and gain (m) register contents are
shown in Table 11 to Table 13.
Table 10. Register Selection
REG1
REG0
Register
Selected
1
1
Input data register (x1)
1
0
Offset register (c)
0
1
Gain register (m)
0
0
Special function registers (SFRs)
Table 11. AD5390/AD5392 DAC Data Format
(REG1 = 1, REG0 = 1)
DB13 to DB0
11 1111
1111
1111
11 1111
1111
1110
10 0000
0000
0001
10 0000
0000
0000
01 1111
1111
1111
00 0000
0000
0001
00 0000
0000
0000
DAC Output (V)
2 V
REF
× (16383/16384)
2 V
REF
× (16382/16384)
2 V
REF
× (8193/16384)
2 V
REF
× (8192/16384)
2 V
REF
× (8191/16384)
2 V
REF
× (1/16384)V
0
Table 12. AD5390/AD5392 Offset Data Format
(REG1 = 1, REG0 = 0)
DB13 to DB0
111111
1111
1111
111111
1111
1110
100000
0000
0001
100000
0000
0000
011111
1111
1111
000000
0000
0001
000000
0000
0000
Offset (LSB)
+8192
+8191
+1
+0
–1
–8191
–8192
Table 13. AD5390/AD5392 Gain Data Format
(REG1 = 0, REG0 = 1)
DB13 to DB0
11 1111
1111
10 1111
1111
01 1111
1111
00 1111
1111
00 0000
0000
Gain Factor
1
0.75
0.5
0.25
0
1110
1110
1110
1110
0000
DATA DECODING—AD5391
The AD5391contains an internal 12-bit data bus. The input
data is decoded depending on the value loaded to the REG1
and REG0 bits of the input serial register. The input data from
the serial input register is loaded into the addressed DAC input
register, offset (c) register, or gain (m) register. The format data
and the offset (c) and gain (m) register contents are shown in
Table 14 to Table 16.
Table 14. AD5391 DAC Data Format (REG1 = 1, REG0 = 1)
DB11 to DB0
1111
1111
1111
1111
1111
1110
1000
0000
0001
1000
0000
0000
0111
1111
1111
0000
0000
0001
0000
0000
0000
DAC Output (V)
2 V
REF
× (4095/4096)
2 V
REF
× (4094/4096)
2 V
REF
× (2049/4096)
2 V
REF
× (2048/4096)
2 V
REF
× (2047/4096)
2 V
REF
× (1/4096)
0
Table 15. AD5391 Offset Data Format (REG1 = 1, REG0 = 0)
DB11 to DB0
1111
1111
1111
1111
1111
1110
1000
0000
0001
1000
0000
0000
0111
1111
1111
0000
0000
0001
0000
0000
0000
Offset (LSB)
+2048
+2047
+1
+0
–1
–2047
–2048
Table 16. AD5391 Gain Data Format (REG1 = 0, REG0 = 1)
DB11 to DB0
1111
1111
1110
1011
1111
1110
0111
1111
1110
0011
1111
1110
0000
0000
0000
Gain Factor
1
0.75
0.5
0.25
0
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