參數(shù)資料
型號： AD5391BST-5-REEL
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： 8-/16-Channel, 3 V/5 V, Serial Input, Single- Supply, 12-/14-Bit Voltage Output DACs
中文描述： SERIAL INPUT LOADING, 6 us SETTLING TIME, 12-BIT DAC, PQFP52
封裝： 10 X 10 MM, MS-026BCC, LQFP-52
文件頁數(shù)： 10/44頁
文件大?。?/td> 1319K
代理商： AD5391BST-5-REEL
AD5390/AD5391/AD5392
TIMING CHARACTERISTICS:
SERIAL SPI-, QSPI-, MICROWIRE-, AND DSP-COMPATIBLE INTERFACE
DV
DD
= 2 V to 5.5 V; AV
DD
= 2.7 V to 5.5 V; AGND = DGND = 0 V. All specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 6. 3-Wire Serial Interface
1
Parameter
2, 3
Limit at T
MIN
, T
MAX
Unit
t
1
33
ns min
t
2
13
ns min
t
3
13
ns min
t
4
13
ns min
t
54
13
ns min
t
6
4
33
ns min
t
7
10
ns min
t
7A
50
ns min
t
8
5
ns min
t
9
4.5
ns min
t
10
4
30
ns max
t
11
670
ns max
t
12
4
20
ns min
t
13
20
ns min
t
14
100
ns max
t
15
0
ns min
t
16
100
ns min
t
17
8
μs typ
t
17
6
μs typ
t
18
20
ns min
t
19
12
μs max
t
205
20
ns max
t
214
5
ns min
t
224
8
ns min
t
234
20
ns min
Rev. A | Page 10 of 44
Description
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
24
th
SCLK falling edge to SYNC falling edge
Minimum SYNC low time
Minimum SYNC high time
Minimum SYNC high time in readback mode
Data setup time
Data hold time
24
th
SCLK falling edge to BUSY falling edge
BUSY pulse width low (single channel update)
24
th
SCLK falling edge to LDAC falling edge
LDAC pulse width low
BUSY rising edge to DAC output response time
BUSY rising edge to LDAC falling edge
LDAC falling edge to DAC output response time
DAC output settling time, AD5390/AD5392
DAC output settling time, AD5391
CLR pulse width low
CLR pulse activation time
SCLK rising edge to SDO valid
SCLK falling edge to SYNC rising edge
SYNC rising edge to SCLK rising edge
SYNC rising edge to LDAC falling edge
1
Guaranteed by design and characterization, not production tested.
2
All input signals are specified with tr = tf = 5 ns (10% to 90% of V
CC
) and timed from a voltage level of 1.2 V.
3
See
, F
,
and
.
Figure 2 igure 3 Figure 4,
Figure 5
4
Standalone mode only.
5
Daisy-chain mode only.
相關(guān)PDF資料
PDF描述
AD5392 8-/16-Channel, 3 V/5 V, Serial Input, Single- Supply, 12-/14-Bit Voltage Output DACs
AD5392BST-3 8-/16-Channel, 3 V/5 V, Serial Input, Single- Supply, 12-/14-Bit Voltage Output DACs
AD5392BST-5 8-/16-Channel, 3 V/5 V, Serial Input, Single- Supply, 12-/14-Bit Voltage Output DACs
AD5392BST-5-REEL Quad 12-bit 125MSPS ADC with serialized LVDS output 64-VQFN -40 to 85
AD5390BCP-3 8-/16-Channel, 3 V/5 V, Serial Input, Single- Supply, 12-/14-Bit Voltage Output DACs
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參數(shù)描述
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