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| 型號： | AD538BD |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運動控制電子 |
| 英文描述： | Real-Time Analog Computational Unit ACU |
| 中文描述： | ANALOG MULTIPLE FUNCTIONS, 0.4 MHz BAND WIDTH, CDIP18 |
| 封裝： | SIDE BRAZED, CERAMIC, DIP-18 |
| 文件頁數(shù)： | 9/11頁 |
| 文件大?。?/td> | 167K |
| 代理商： | AD538BD |
AD538
–9–
REV. C
ANALOG COMPUTATION OF POWERS AND ROOTS
It is often necessary to raise the quotient of two input signals to
a power or take a root. This could be squaring, cubing, square-
rooting or exponentiation to some noninteger power. Examples
include power series generation. With the AD538, only one or
two external resistors are required to set ANY desired power,
over the range of 0.2 to 5. Raising the basic quantity V
Z
/V
X
to a
power greater than one requires that the gain of the AD538’s log
ratio subtractor be increased, via an external resistor between
pins A and D. Similarly, a voltage divider that attenuates the log
ratio output between points B and C will program the power to
a value less than one.
3
12
18
17
2
10
15
8
V
Y
( V
m
REF
V
Z
R
A
V
O
V
Z
V
Y
V
REF
V
X
B
C
A
D
R
A
=M –1
V
R
B
= R
C
#
200
V
POWERS
m R
A
2 196
V
3 97.6
V
4 64.9
V
5 48.7
V
3
12
2
10
15
8
V
Y
( V
m
REF
V
V
O
V
Z
V
Y
V
REF
V
X
B
C
R
B
R
C
ROOTS
m R
B
R
C
1/2 100
V
100
V
1/3 100
V
49.9
V
1/4 150
V
49.9
V
1/5 162
V
40.2
V
R
B
R
C
= M
1
Figure 15. Basic Configurations and Transfer Functions
+15V
–15V
ID1
V
OUT
= 1V
V
IN
1V
*
*
R
C
100
V
R
B
100
V
V
OUT
7
1
8
6
4
2
3
+V
S
IN4148
IN4148
AD OP-07
OR AD611
(V
TAP
TO –V
S
)
–V
S
20k
V
5k
V
20k
V
ABSOLUOPTIONAL
10k
V
V
IN
+2V
1k
V
1k
V
100
V
SCALE FACTOR
TRIM
RATIO MATCH 1% METAL FILM
RESISTORS FOR BEST ACCURACY
*
25k
V
25k
V
LOG
RATIO
100
V
25k
V
25k
V
ANTILOG
LOG
OUTPUT
100
V
AD538
INTERNAL
VOLTAGE
REFERENCE
I
V
O
I
Z
V
Z
B
+10V
I
Y
A
D
I
X
V
X
C
PWR
GND
SIGNAL
GND
V
Y
1
18
17
16
15
14
13
12
11
10
2
3
4
5
6
7
8
9
+2V
V
OS
20k
V
Figure 16. Square Root Circuit
SQUARE ROOT OPERATION
The explicit square root circuit of Figure 16 illustrates a precise
method for performing a real-time square root computation. For
added flexibility and accuracy, this circuit has a scale factor
adjustment.
The actual square rooting operation is performed in this circuit
by raising the quantity V
Z
/V
X
to the one-half power via the
resistor divider network consisting of resistors R
B
and R
C
. For
maximum linearity, the two resistors should be 1% (or better)
ratio-matched metal film types.
One volt scaling is achieved by dividing-down the 2 V reference
and applying approximately 1 V to both the V
Y
and V
X
inputs.
In this circuit, the V
X
input is intentionally set low, to about
0.95 V, so that the V
Y
input can be adjusted high, permitting a
±
5% scale factor trim. Using this trim scheme, the output volt-
age will be within
±
3 mV
±
0.2% of the ideal value over a 10 V
to 1 mV input range (80 dB). For a decreased input dynamic
range of 10 mV to 10 V (60 dB) the error is even less; here the
output will be within
±
2 mV
±
0.2% of the ideal value. The
bandwidth of the AD538 square root circuit is approximately
280 kHz with a 1 V p-p sine wave with a +2 V dc offset.
This basic circuit may also be used to compute the cube, fourth
or fifth roots of an input waveform. All that is required for a
given root is that the correct ratio of resistors, R
C
and R
B
, be
selected such that their sum is between 150
and 200
.
The optional absolute value circuit shown preceding the AD538
allows the use of bipolar input voltages. Only one op amp is
required for the absolute value function because the I
Z
input of
the AD538 functions as a summing junction. If it is necessary to
preserve the sign of the input voltage, the polarity of the op amp
output may be sensed and used after the computation to switch
the sign bit of a D.V.M. chip.
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