參數(shù)資料
型號: AD5382BST-3-REEL
廠商: ANALOG DEVICES INC
元件分類: DAC
英文描述: CONNECTOR ACCESSORY
中文描述: PARALLEL, WORD INPUT LOADING, 8 us SETTLING TIME, 14-BIT DAC, PQFP100
封裝: 14 X 14 MM, MS-026BED, LQFP-100
文件頁數(shù): 11/40頁
文件大?。?/td> 616K
代理商: AD5382BST-3-REEL
AD5382
PARALLEL INTERFACE
Table 8. DV
DD
= 2.7 V to 5.5 V; AV
DD
= 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications
T
MIN
to T
MAX
, unless otherwise noted
Parameter
1
,
2
,
3
Limit at T
MIN
, T
MAX
Unit
t
0
4.5
ns min
t
1
4.5
ns min
t
2
20
ns min
t
3
20
ns min
t
4
0
ns min
t
5
0
ns min
t
6
4.5
ns min
t
7
4.5
ns min
t
8
20
ns min
t
94
700
ns min
t
104
30
ns max
t
114, 5
670
ns max
t
12
30
ns min
t
13
20
ns min
t
14
100
ns max
t
15
20
ns min
t
16
0
ns min
t
17
100
ns min
t
18
8
μs typ
t
19
20
ns min
t
20
35
μsmax
Rev. 0 | Page 11 of 40
Description
REG0, REG1, address to WR rising edge setup time
REG0, REG1, address to WR rising edge hold time
CS pulse width low
WR pulse width low
CS to WR falling edge setup time
WR to CS rising edge hold time
Data to WR rising edge setup time
Data to WR rising edge hold time
WR pulse width high
Minimum WR cycle time (single-channel write)
WR rising edge to BUSY falling edge
BUSY pulse width low (single-channel update)
WR rising edge to LDAC falling edge
LDAC pulse width low
BUSY rising edge to DAC output response time
LDAC rising edge to WR rising edge
BUSY rising edge to LDAC falling edge
LDAC falling edge to DAC output response time
DAC output settling time
CLR pulse width low
CLR pulse activation time
1
Guaranteed by design and characterization, not production tested.
2
All input signals are specified with t
R
= t
R
= 5 ns (10% to 90% of DV
DD
) and timed from a voltage level of 1.2 V.
3
See Figure 7.
4
See Figure 29.
5
Measured with the load circuit of Figure 2.
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