參數(shù)資料
型號(hào)： AD5380BST-3
廠商： ANALOG DEVICES INC
元件分類(lèi)： DAC
英文描述： 40-Channel, 3V/5V Single Supply, 14-Bit, Voltage-Output DAC
中文描述： PARALLEL, WORD INPUT LOADING, 8 us SETTLING TIME, 14-BIT DAC, PQFP100
封裝： 14 X 14 MM, MS-026BED, LQFP-100
文件頁(yè)數(shù)： 26/34頁(yè)
文件大?。?/td> 975K
代理商： AD5380BST-3
PRELIMINARY TECHNICAL DATA
REV. PrF 09/2003
–26–
AD5380
3-Byte Mode
Three byte mode allows the user update more than one channel in a write sequence without having to write the device
address byte each time. The device address byte is only required once and subsequent channel updates require the pointer
byte and the data bytes. In three byte mode the user begins with an address byte (R/
W
= 0) after which the DAC will
acknowledge that it is prepared to receive data by pulling SDA low. The address byte is followed by the pointer
byte, this addresses the specific channel in the DAC to be addressed and is also acknowledged by the DAC. This is
then followed by the two data bytes. REG1 and REG0 determine the register to be updated.
If a STOP condition is not sent following the data bytes another channel can be updated by sending a new pointer
byte followed by the data bytes. This mode only requires 3-bytes to be sent to update any channel once the device
has been initially addressed and reduces the software overhead in updating the AD5380 channels. A STOP condition
at any time exits this mode. Figure 12 shows a typical configuration.
Figure 12 . 3-Byte AD5380, I2C Write Operation
0
A0
ACK
BY
AD538X
MSB
POINTER BYTE FOR CHANNEL “N”
A5
A4
A3
A2
A1
0
MOST SIGNIFICANT DATA BYTE
LEAST SIGNIFICANT DATA BYTE
SCL
SDA
REG1
LSB
MSB
LSB
ACK
BY
AD538X
ACK
BY
AD538X
REG0
MSB
1
0
1
0
1
AD0
R/
W
ACK
BY
AD538X
ADDRESS BYTE
START
COND
BY
MASTER
SCL
SDA
AD1
0
A0
ACK
BY
AD538X
MSB
A5
A4
A3
A2
A1
0
MOST SIGNIFICANT DATA BYTE
LEAST SIGNIFICANT DATA BYTE
SCL
SDA
REG1
LSB
MSB
LSB
ACK
BY
AD538X
ACK
BY
AD538X
STOP
COND
BY
MASTER
REG0
MSB
SCL
SDA
DATA FOR CHANNEL “N”
POINTER BYTE FOR CHANNEL “NEXT CHANNEL”
DATA FOR CHANNEL “NEXT CHANNEL”
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