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參數(shù)資料
型號(hào): AD5371BBCZ-REEL
廠商: Analog Devices Inc
文件頁數(shù): 25/29頁
文件大?。?/td> 0K
描述: IC DAC 14BIT 40CH SER 100-CSPBGA
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 1
設(shè)置時(shí)間: 20µs
位數(shù): 14
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 40
電壓電源: 模擬和數(shù)字,雙 ±
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-LFBGA,CSPBGA
供應(yīng)商設(shè)備封裝: 100-CSBGA(10x10)
包裝: 標(biāo)準(zhǔn)包裝
輸出數(shù)目和類型: 40 電壓,單極;40 電壓,雙極
采樣率(每秒): *
其它名稱: AD5371BBCZ-REELDKR
AD5371
Rev. B | Page 4 of 28
SPECIFICATIONS
PERFORMANCE SPECIFICATIONS
DVCC = 2.5 V to 5.5 V; VDD = 9 V to 16.5 V; VSS = 16.5 V to 8 V; VREF = 3 V; AGND = DGND = SIGGNDx = 0 V; CL = open circuit;
RL = open circuit; gain (M), offset (C), and DAC offset registers at default values; temperature range for the AD5371 is 40°C to +85°C; all
specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
Min
Typ1
Max
Unit
Test Conditions/Comments1
ACCURACY
Resolution
14
Bits
Integral Nonlinearity (INL)
1
+1
LSB
Differential Nonlinearity (DNL)
1
+1
LSB
Guaranteed monotonic by design
Zero-Scale Error
10
+10
mV
Before calibration
Full-Scale Error
10
+10
mV
Before calibration
Gain Error
0.1
% FSR
Zero-Scale Error2
1
LSB
After calibration
Full-Scale Error2
1
LSB
After calibration
Span Error of Offset DAC
35
+35
mV
See the Offset DACs section for details
VOUTx Temperature Coefficient
(VOUT0 to VOUT39)
5
ppm
FSR/°C
Includes linearity, offset, and gain drift
DC Crosstalk2
120
μV
Typically 20 μV; measured channel at midscale,
full-scale change on any other channel
REFERENCE INPUTS (VREF0, VREF1, VREF2)2
VREFx Input Current
10
+10
μA
Per input; typically ±30 nA
VREFx Range
2
5
V
±2% for specified operation
SIGGND INPUTS (SIGGND0 TO SIGGND4)2
DC Input Impedance
50
Typically 55 kΩ
Input Range
0.5
+0.5
V
SIGGNDx Gain
0.995
1.005
OUTPUT CHARACTERISTICS2
Output Voltage Range
VSS + 1.4
VDD 1.4
V
ILOAD = 1 mA
Nominal Output Voltage Range
4
+8
V
Short-Circuit Current
15
mA
VOUTx to DVCC, VDD, or VSS
Load Current
1
+1
mA
Capacitive Load
2200
pF
DC Output Impedance
0.5
Ω
DIGITAL INPUTS
Input High Voltage
1.7
V
DVCC = 2.5 V to 3.6 V
2.0
V
DVCC = 3.6 V to 5.5 V
Input Low Voltage
0.8
V
DVCC = 2.5 V to 5.5 V
Input Current
1
+1
μA
Excluding CLR pin
CLR High Impedance Leakage Current
20
+20
μA
Input Capacitance2
10
pF
DIGITAL OUTPUTS (SDO, BUSY)
Output Low Voltage
0.5
V
Sinking 200 μA
Output High Voltage (SDO)
DVCC 0.5
V
Sourcing 200 μA
SDO High Impedance Leakage Current
5
+5
μA
High Impedance Output Capacitance2
10
pF
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