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參數(shù)資料
| 型號： | AD5336BRU-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 10BIT QUAD VOUT 28-TSSOP |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標準包裝： | 1,000 |
| 設置時間： | 7µs |
| 位數(shù)： | 10 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 4.5mW |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 28-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電壓，單極；4 電壓，雙極 |
| 采樣率（每秒）： | 143k |
REV. 0
AD5334/AD5335/AD5336/AD5344
–13–
IDD – A
FREQUENCY
300
350
600
400
450
500
550
VDD = 5V
VDD = 3V
Figure 23. IDD Histogram with VDD =
3 V and VDD = 5 V
FULL-SCALE
ERROR
–
%FSR
0
–0.2
0
1
2
345
6
VDD = 5V
TA = 25 C
VREF – V
–0.1
0.1
0.2
0.3
0.4
Figure 26. Full-Scale Error vs. VREF
500ns/DIV
V
OUT
–
Volts
0.919
0.920
0.921
0.922
0.923
0.924
0.925
0.926
0.927
0.928
0.929
Figure 24. AD5344 Major-Code Tran-
sition Glitch Energy
750ns/DIV
1mV/DIV
Figure 27. DAC-DAC Crosstalk
FREQUENCY – kHz
10
–40
0.01
–20
–30
0
–10
dB
0.1
1
10
100
1k
10k
–50
–60
Figure 25. Multiplying Bandwidth
(Small-Signal Frequency Response)
FUNCTIONAL DESCRIPTION
The AD5334/AD5335/AD5336/AD5344 are quad resistor-
string DACs fabricated on a CMOS process with resolutions of
8, 10, 10, and 12 bits, respectively. They are written to using a
parallel interface. They operate from single supplies of 2.5 V to
5.5 V and the output buffer ampliers offer rail-to-rail output
swing. The gain of the buffer ampliers in the AD5334 and
AD5336 can be set to 1 or 2 to give an output voltage range of
0 to VREF or 0 to 2 VREF. The AD5335 and AD5344 have out-
put buffers with unity gain.
The devices have a power-down feature that reduces current
consumption to only 80 nA @ 3 V.
Digital-to-Analog Section
The architecture of one DAC channel consists of a reference
buffer and a resistor-string DAC followed by an output buffer
amplier. The voltage at the VREF pin provides the reference
voltage for the DAC. Figure 28 shows a block diagram of the
DAC architecture. Since the input coding to the DAC is
straight binary, the ideal output voltage is given by:
VV
D
Gain
OUT
REF
N
=×
×
2
where:
D = decimal equivalent of the binary code which is loaded to
the DAC register:
0–255 for AD5334 (8 Bits)
0–1023 for AD5335/AD5336 (10 Bits)
0–4095 for AD5344 (12 Bits)
N = DAC resolution
Gain = Output Amplier Gain (1 or 2)
VOUT
GAIN
DAC
REGISTER
INPUT
REGISTER
RESISTOR
STRING
OUTPUT
BUFFER AMPLIFIER
VREF
Figure 28. Single DAC Channel Architecture
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| AD5336BRUZ | 功能描述:IC DAC 10BIT QUAD VOUT 28-TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:50 系列:- 設置時間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應商設備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁面:1398 (CN2011-ZH PDF) |
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| AD5337 | 制造商:AD 制造商全稱:Analog Devices 功能描述:2.5 V to 5.5 V, 250 UA, 2-Wire Interface Dual-Voltage Output, 8-/10-/12-Bit DACs |
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