參數(shù)資料
型號(hào): AD5327BRUZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 8/28頁(yè)
文件大?。?/td> 0K
描述: IC DAC 12BIT QUAD 2.5V 16-TSSOP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 1
設(shè)置時(shí)間: 8µs
位數(shù): 12
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 4
電壓電源: 單電源
功率耗散(最大): 4.5mW
工作溫度: -40°C ~ 105°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 管件
輸出數(shù)目和類(lèi)型: 4 電壓,單極;4 電壓,雙極
采樣率(每秒): 125k
產(chǎn)品目錄頁(yè)面: 782 (CN2011-ZH PDF)
AD5307/AD5317/AD5327
Rev. C | Page 16 of 28
OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating output
voltages to within 1 mV of either rail. Its actual range depends
on the value of VREF, GAIN, offset error, and gain error.
If a gain of 1 is selected (GAIN = 0), the output range is 0.001 V
to VREF.
If a gain of 2 is selected (GAIN = 1), the output range is 0.001 V
to 2 VREF. Because of clamping, however, the maximum output
is limited to VDD 0.001 V.
The output amplifier is capable of driving a load of 2 kΩ to GND
or VDD in parallel with 500 pF to GND or VDD. The source and
sink capabilities of the output amplifier can be seen in Figure 16.
The slew rate is 0.7 V/μs, with a half-scale settling time to
±0.5 LSB (at eight bits) of 6 μs.
POWER-ON RESET
The AD5307/AD5317/AD5327 are each provided with a power-
on reset function so that they power up in a defined state. The
power-on state is
Normal operation
Reference inputs unbuffered
0 V to VREF output range
Output voltage set to 0 V
Both input and DAC registers are filled with 0s until a valid
write sequence is made to the device. This is particularly useful
in applications where it is important to know the state of the
DAC outputs while the device is powering up.
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