參數資料
型號: AD5325BRMZ
廠商: Analog Devices Inc
文件頁數: 23/24頁
文件大小: 0K
描述: IC DAC 12BIT 2WIRE I2C 10-MSOP
產品培訓模塊: Data Converter Fundamentals
DAC Architectures
標準包裝: 50
設置時間: 6µs
位數: 12
數據接口: I²C,串行
轉換器數目: 4
電壓電源: 單電源
功率耗散(最大): 5mW
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應商設備封裝: 10-MSOP
包裝: 管件
輸出數目和類型: 4 電壓,單極;4 電壓,雙極
采樣率(每秒): 125k
產品目錄頁面: 782 (CN2011-ZH PDF)
AD5305/AD5315/AD5325
Rev. G | Page 8 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
10
9
8
7
6
1
2
3
4
5
GND
SDA
SCL
REFIN
A0
AD5305/
AD5315/
AD5325
TOP VIEW
(Not to Scale)
VDD
VOUTA
VOUTB
VOUTC
VOUTD
00
93
0-
00
3
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
VDD
Power Supply Input. These parts can be operated from 2.5 V to 5.5 V and the supply should be decoupled to GND.
2
VOUTA
Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
3
VOUTB
Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
4
VOUTC
Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
5
REFIN
Reference Input Pin for All Four DACs. It has an input range from 0.25 V to VDD.
6
VOUTD
Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
7
GND
Ground Reference Point for All Circuitry on the Part.
8
SDA
Serial Data Line. This is used in conjunction with the SCL line to clock data into or out of the 16-bit input shift
register. It is a bidirectional open-drain data line that should be pulled to the supply with an external pull-up
resistor.
9
SCL
Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 16-bit input shift
register. Clock rates of up to 400 kb/s can be accommodated in the 2-wire interface.
10
A0
Address Input. Sets the least significant bit of the 7-bit slave address.
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