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參數(shù)資料
| 型號： | AD5320BRT-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/20頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 12BIT R-R W/BUFF SOT23-6 |
| 產品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 1 |
| 設置時間： | 8µs |
| 位數(shù)： | 12 |
| 數(shù)據接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-6 |
| 供應商設備封裝： | SOT-23-6 |
| 包裝： | 剪切帶 (CT) |
| 輸出數(shù)目和類型： | 1 電壓，雙極 |
| 采樣率（每秒）： | 125k |
| 其它名稱： | AD5320BRT-REEL7CT |
AD5320
Rev. C | Page 3 of 20
SPECIFICATIONS
VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 1.
B Version1
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
STATIC PERFORMANCE2
Resolution
12
Bits
Relative Accuracy
±16
LSB
See Figure 5
Differential Nonlinearity
±1
LSB
Guaranteed monotonic by design (see Figure 6)
Zero-Code Error
5
40
mV
All zeroes loaded to DAC register (see Figure 9)
Full-Scale Error
0.15
1.25
% of FSR
All ones loaded to DAC register (see Figure 9)
Gain Error
±1.25
% of FSR
Zero-Code Error Drift
20
μV/°C
Gain Temperature Coefficient
5
ppm of FSR/°C
OUTPUT CHARACTERISTICS3
Output Voltage Range
0
VDD
V
Output Voltage Settling Time
8
10
μs
1/4 scale to 3/4 scale change (400 hex to C00 hex)
12
μs
RL = 2 kΩ, CL = 500 pF
Slew Rate
1
V/μs
Capacitive Load Stability
470
pF
RL = ∞
1000
pF
RL = 2 kΩ
Digital-to-Analog Glitch Impulse
20
nV-s
1 LSB change around major carry (see Figure 22)
Digital Feedthrough
0.5
nV-s
DC Output Impedance
1
Ω
Short Circuit Current
50
mA
VDD = 5 V
20
mA
VDD = 3 V
Power-Up Time
2.5
μs
Coming out of power-down mode, VDD = 5 V
5
μs
Coming out of power-down mode, VDD = 3 V
LOGIC INPUTS3
Input Current
±1
μA
VINL, Input Low Voltage
0.8
V
VDD = 5 V
VINL, Input Low Voltage
0.6
V
VDD = 3 V
VINH, Input High Voltage
2.4
V
VDD = 5 V
VINH, Input High Voltage
2.1
V
VDD = 3 V
Pin Capacitance
3
pF
POWER REQUIREMENTS
VDD
2.7
5.5
V
IDD (Normal Mode)
DAC active and excluding load current
VDD = 4.5 V to 5.5 V
140
250
μA
VIH = VDD and VIL = GND
VDD = 2.7 V to 3.6 V
115
200
μA
VIH = VDD and VIL = GND
IDD (All Power-Down Modes)
VDD = 4.5 V to 5.5 V
0.2
1
μA
VIH = VDD and VIL = GND
VDD = 2.7 V to 3.6 V
0.05
1
μA
VIH = VDD and VIL = GND
POWER EFFICIENCY
IOUT/IDD
93
%
ILOAD = 2 mA, VDD = 5 V
1 Temperature range is as follows: B Version: 40°C to +105°C.
2 Linearity calculated using a reduced code range of 48 to 4047; output unloaded.
3 Guaranteed by design and characterization, not production tested.
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