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參數(shù)資料
| 型號： | AD5317BRUZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/28頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 10BIT QUAD W/BUFF 16TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時間： | 7µs |
| 位數(shù)： | 10 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 輸出數(shù)目和類型： | 4 電壓，單極；4 電壓，雙極 |
| 采樣率（每秒）： | 143k |
| 其它名稱： | AD5317BRUZREEL7DKR |
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AD5307/AD5317/AD5327
Rev. C | Page 15 of 28
FUNCTIONAL DESCRIPTION
The AD5307/AD5317/AD5327 are quad resistor-string DACs
fabricated on a CMOS process with resolutions of 8, 10, and 12
bits respectively. Each contains four output buffer amplifiers
and is written to via a 3-wire serial interface. They operate from
single supplies of 2.5 V to 5.5 V, and the output buffer amplifiers
provide rail-to-rail output swing with a slew rate of 0.7 V/μs.
DAC A and DAC B share a common reference input, VREFAB.
DAC C and DAC D share a common reference input, VREFCD.
Each reference input can be buffered to draw virtually no
current from the reference source, or can be unbuffered to give
a reference input range of 0.25 V to VDD. The devices have a
power-down mode in which all DACs can be completely turned
off with a high impedance output.
DIGITAL-TO-ANALOG SECTION
The architecture of one DAC channel consists of a resistor-
string DAC followed by an output buffer amplifier. The voltage
at the VREF pin provides the reference voltage for the
corresponding DAC. Figure 31 shows a block diagram of the
DAC architecture. Because the input coding to the DAC is
straight binary, the ideal output voltage is given by
N
REF
OUT
D
V
2
×
=
where:
D is the decimal equivalent of the binary code that is loaded to
the DAC register:
0 to 255 for AD5307 (8 bits).
0 to 1023 for AD5317 (10 bits).
0 to 4095 for AD5327 (12 bits).
N is the DAC resolution.
INPUT
REGISTER
DAC
REGISTER
RESISTOR
STRING
OUTPUT
BUFFER AMPLIFIER
REFERENCE
BUFFER
BUF
GAIN MODE
(GAIN = 1 OR 2)
VREFAB
VOUTA
02067-031
Figure 31. Single DAC Channel Architecture
RESISTOR STRING
The resistor string section is shown in Figure 32. It is simply a
string of resistors, each of value R. The digital code loaded to
the DAC register determines at which node on the string the
voltage is tapped off to be fed into the output amplifier. The
voltage is tapped off by closing one of the switches connecting
the string to the amplifier. Because it is a string of resistors, it is
guaranteed monotonic.
DAC REFERENCE INPUTS
There is a reference pin for each pair of DACs. The reference
inputs are buffered but can also be individually configured as
unbuffered. The advantage with the buffered input is the high
impedance it presents to the voltage source driving it. However,
if the unbuffered mode is used, the user can have a reference
voltage as low as 0.25 V and as high as VDD, because there is no
restriction due to headroom and footroom of the reference
amplifier.
R
TO OUTPUT
AMPLIFIER
02067-032
Figure 32. Resistor String
If there is a buffered reference in the circuit (for example, REF192),
there is no need to use the on-chip buffers of the AD5307/AD5317/
AD5327. In unbuffered mode, the input impedance is still large
at typically 90 kΩ per reference input for 0 V to VREF mode and
45 kΩ or 0 V to 2 VREF mode.
The buffered/unbuffered option is controlled by the BUF bit in
the data-word. The BUF bit setting applies to whichever DAC is
selected.
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