參數(shù)資料
型號(hào): AD5308
廠商: Analog Devices, Inc.
英文描述: 2.5 V to 5.5 V Octal Voltage Output 8-/10-/12-Bit DACs in 16-Lead TSSOP
中文描述: 2.5 V至5.5 V電壓輸出8-/10-/12-Bit八路數(shù)模轉(zhuǎn)換器的16引腳TSSOP
文件頁(yè)數(shù): 3/19頁(yè)
文件大小: 308K
代理商: AD5308
REV. B
AD5308/AD5318/AD5328
–3–
AC CHARACTERISTICS
1
(V
DD
= 2.5 V to 5.5 V; R
L
= 2 k to GND; C
L
= 200 pF to GND; all specifications T
MIN
to T
MAX
, unless
otherwise noted.)
A, B Version
3
Min
Typ
Max
Unit
Parameter
2
Conditions/Comments
Output Voltage Settling Time
AD5308
AD5318
AD5328
Slew Rate
Major-Code Change Glitch Energy
Digital Feedthrough
Digital Crosstalk
Analog Crosstalk
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
V
REF
= V
DD
= 5 V
1/4 Scale to 3/4 Scale Change (0x40 to 0xC0)
1/4 Scale to 3/4 Scale Change (0x100 to 0x300)
1/4 Scale to 3/4 Scale Change (0x400 to 0xC00)
6
7
8
0.7
12
0.5
0.5
1
3
200
–70
8
9
10
μ
s
μ
s
μ
s
V/
μ
s
nV-s
nV-s
nV-s
nV-s
nV-s
kHz
dB
1 LSB Change around Major Carry
V
REF
= 2 V
±
0.1 V p-p. Unbuffered Mode.
V
REF
= 2.5 V
±
0.1 V p-p. Frequency = 10 kHz.
NOTES
1
Guaranteed by design and characterization; not production tested.
2
See the Terminology section.
3
Temperature range (A, B Version): –40
°
C to +105
°
C; typical at +25
°
C.
Specifications subject to change without notice.
TIMING CHARACTERISTICS
1, 2, 3
A, B Version
Parameter
Limit at T
MIN
, T
MAX
t
1
33
t
2
13
t
3
13
t
4
13
t
5
5
t
6
4.5
t
7
0
t
8
50
t
9
20
t
10
20
t
11
0
Unit
Conditions/Comments
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
SCLK Cycle Time
SCLK High Time
SCLK Low Time
SYNC
to SCLK Falling Edge Setup Time
Data Setup Time
Data Hold Time
SCLK Falling Edge to
SYNC
Rising Edge
Minimum
SYNC
High Time
LDAC
Pulsewidth
SCLK Falling Edge to
LDAC
Rising Edge
SCLK Falling Edge to
LDAC
Falling Edge
NOTES
1
Guaranteed by design and characterization; not production tested.
2
All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
3
See Figures 2 and 3.
Specifications subject to change without notice.
SCLK
SYNC
DIN
DB15
DB0
LDAC
1
LDAC
2
NOTES
1
ASYNCHRONOUS LDAC UPDATE MODE
2
SYNCHRONOUS LDAC UPDATE MODE
t
1
t
2
t
8
t
3
t
4
t
5
t
6
t
9
t
11
t
7
t
10
Figure 1. Serial Interface Timing Diagram
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