參數(shù)資料
型號: AD5308
廠商: Analog Devices, Inc.
英文描述: 2.5 V to 5.5 V Octal Voltage Output 8-/10-/12-Bit DACs in 16-Lead TSSOP
中文描述: 2.5 V至5.5 V電壓輸出8-/10-/12-Bit八路數(shù)模轉(zhuǎn)換器的16引腳TSSOP
文件頁數(shù): 2/19頁
文件大?。?/td> 308K
代理商: AD5308
REV. B
–2–
AD5308/AD5318/AD5328–SPECIFICATIONS
GND; C
L
= 200 pF to GND; all specifications T
MIN
to T
MAX
, unless otherwise noted.)
(V
DD
= 2.5 V to 5.5 V; V
REF
= 2 V; R
L
= 2 k to
A Version
2
Typ
B Version
2
Typ
Parameter
1
Min
Max
Min
Max
Unit
Conditions/Comments
DC PERFORMANCE
3, 4
AD5308
Resolution
Relative Accuracy
Differential Nonlinearity
AD5318
Resolution
Relative Accuracy
Differential Nonlinearity
AD5328
Resolution
Relative Accuracy
Differential Nonlinearity
Offset Error
Gain Error
Lower Deadband
5
8
8
Bits
LSB
LSB
±
0.15
±
0.02
±
1
±
0.25
±
0.15
±
0.02
±
0.75
±
0.25
Guaranteed Monotonic by Design over All Codes
10
10
Bits
LSB
LSB
±
0.5
±
0.05
±
4
±
0.50
±
0.5
±
0.05
±
3
±
0.50
Guaranteed Monotonic by Design over All Codes
12
12
Bits
LSB
LSB
mV
% of FSR
mV
±
2
±
0.2
±
5
±
0.30
10
±
16
±
1.0
±
60
±
1.25
60
±
2
±
0.2
±
5
±
0.30
10
±
12
±
1.0
±
60
±
1.25
60
Guaranteed Monotonic by Design over All Codes
V
DD
= 4.5 V, Gain = +2. See Figures 2 and 3.
V
= 4.5 V, Gain = +2. See Figures 2 and 3.
See Figure 2. Lower deadband exists only if offset
error is negative.
See Figure 3. Upper deadband exists only if V
REF
=
V
DD
and offset plus gain error is positive.
Upper Deadband
5
10
60
10
60
mV
Offset Error Drift
6
Gain Error Drift
6
DC Power Supply Rejection Ratio
6
DC Crosstalk
–12
–5
–60
200
–12
–5
–60
200
ppm of FSR/
°
C
ppm of FSR/
°
C
dB
μ
V
V
DD
=
±
10%
R
L
= 2 k
to GND or V
DD
DAC REFERENCE INPUTS
6
V
REF
Input Range
1.0
0.25
V
DD
V
DD
1.0
0.25
V
DD
V
DD
V
V
M
k
Buffered Reference Mode
Unbuffered Reference Mode
Buffered Reference Mode and Power-Down Mode
Unbuffered Reference Mode. 0 V to V
REF
Output Range.
Unbuffered Reference Mode. 0 V to 2 V
REF
Output Range.
Frequency = 10 kHz
Frequency = 10 kHz
V
REF
Input Impedance (R
DAC
)
>10.0
45.0
>10.0
45.0
37.0
37.0
18.0
22.0
18.0
22.0
k
Reference Feedthrough
Channel-to-Channel Isolation
–70.0
–75.0
–70.0
–75.0
dB
dB
OUTPUT CHARACTERISTICS
6
Minimum Output Voltage
7
Maximum Output Voltage
7
DC Output Impedance
Short Circuit Current
0.001
V
DD
– 0.001
0.5
25.0
16.0
2.5
5.0
0.001
V
DD
– 0.001
0.5
25.0
16.0
2.5
5.0
V
V
mA
mA
μ
s
μ
s
This is a measure of the minimum and maximum
drive capability of the output amplifier.
V
DD
= 5 V
V
= 3 V
Coming Out of Power-Down Mode. V
DD
= 5 V.
Coming Out of Power-Down Mode. V
DD
= 3 V.
Power-Up Time
LOGIC INPUTS
6
Input Current
V
IL
, Input Low Voltage
±
1
0.8
0.8
0.7
±
1
0.8
0.8
0.7
μ
A
V
V
V
V
V
DD
= 5 V
±
10%
V
DD
= 3 V
±
10%
V
DD
= 2.5 V
V
= 2.5 V to 5.5 V; TTL and CMOS
Compatible
V
IH
, Input High Voltage
1.7
1.7
Pin Capacitance
3.0
3.0
pF
POWER REQUIREMENTS
V
DD
I
DD
(Normal Mode)
8
V
DD
= 4.5 V to 5.5 V
V
DD
= 2.5 V to 3.6 V
2.5
5.5
2.5
5.5
V
V
IH
= V
DD
and V
IL
= GND
All DACs in Unbuffered Mode. In Buffered mode,
extra current is typically x
μ
A per DAC; x = (5
μ
A
+ V
REF
/R
DAC
)/4.
V
IH
= V
DD
and V
IL
= GND
1.0
0.7
1.8
1.5
1.0
0.7
1.8
1.5
mA
mA
I
DD
(Power-Down Mode)
9
V
DD
= 4.5 V to 5.5 V
V
DD
= 2.5 V to 3.6 V
0.4
0.12
1
1
0.4
0.12
1
1
μ
A
μ
A
NOTES
1
See the Terminology section.
2
Temperature range (A, B Version): –40
°
C to +105
°
C; typical at +25
°
C.
3
DC specifications tested with the outputs unloaded unless stated otherwise.
4
Linearity is tested using a reduced code range: AD5308 (Code 8 to Code 255), AD5318 (Code 28 to Code 1023), and AD5328 (Code 115 to Code 4095).
5
This corresponds to x codes. x = deadband voltage/LSB size.
6
Guaranteed by design and characterization; not production tested.
7
For the amplifier output to reach its minimum voltage, offset error must be negative; for the amplifier output to reach its maximum voltage, V
REF
= V
DD
and offset plus gain error
must be positive.
8
Interface inactive. All DACs active. DAC outputs unloaded.
9
All eight DACs powered down.
Specifications subject to change without notice.
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