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參數(shù)資料
| 型號： | AD5306BRUZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 8BIT QUAD W/BUFF 16-TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 96 |
| 設(shè)置時間： | 6µs |
| 位數(shù)： | 8 |
| 數(shù)據(jù)接口： | I²C，串行 |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 4.5mW |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 4 電壓，單極；4 電壓，雙極 |
| 采樣率（每秒）： | 167k |
| 產(chǎn)品目錄頁面： | 782 (CN2011-ZH PDF) |
AD5306/AD5316/AD5326
Rev. F | Page 16 of 24
POWER-ON RESET
The AD5306/AD5316/AD5326 have a power-on reset function
so that they power up in a defined state. The power-on state is
Normal operation
Reference inputs unbuffered
0 V to V
REF
output range
Output voltage set to 0 V
Both input and DAC registers are filled with 0s and remain so
until a valid write sequence is made to the device. This is
particularly useful in applications where it is important to know
the state of the DAC outputs while the device is powering up.
SERIAL INTERFACE
The AD5306/AD5316/AD5326 are controlled via an I2C-
compatible serial bus. These devices are connected to this bus as
slave devices; that is, no clock is generated by the AD5306/
AD5316/AD5326 DACs. This interface is SMBus-compatible
at VDD < 3.6 V.
The AD5306/AD5316/AD5326 has a 7-bit slave address. The
five MSBs are 00011, and the two LSBs are determined by the
state of the A0 and A1 pins. The facility to make hardwired
changes to A0 and A1 allows the user to have up to four of these
devices on one bus.
The 2-wire serial bus protocol operates as follows:
1.
The master initiates data transfer by establishing a start
condition, which is when a high-to-low transition on the
SDA line occurs while SCL is high. The following byte is
the address byte, which consists of the 7-bit slave address
followed by an R/W bit. This bit determines whether data
is read from or written to the slave device.
The slave whose address corresponds to the transmitted
address responds by pulling SDA low during the ninth
clock pulse (this is termed the acknowledge bit). At this
stage, all other devices on the bus remain idle while the
selected device waits for data to be written to or read from
its shift register.
2.
Data is transmitted over the serial bus in sequences of
nine clock pulses (eight data bits followed by an
acknowledge bit). The transitions on the SDA line must
occur during the low period of SCL and remain stable
during the high period of SCL.
3.
When all data bits have been read from or written to, a
stop condition is established. In write mode, the master
pulls the SDA line high during the 10th clock pulse to
establish a stop condition. In read mode, the master issues
a no acknowledge for the ninth clock pulse; that is, the
SDA line remains high. The master then brings the SDA
line low before the 10th clock pulse and then high during
the 10th clock pulse to establish a stop condition.
READ/WRITE SEQUENCE
For the AD5306/AD5316/AD5326, all write access sequences
and most read sequences begin with the device address (with
R/W = 0) followed by the pointer byte. This pointer byte speci-
fies the data format and determines that DAC is being accessed
in the subsequent read/write operation (see Figure 1). In a write
operation, the data follows immediately. In a read operation, the
address is resent with R/W = 1, and the data is then read back.
However, it is also possible to perform a read operation by
sending only the address with R/W = 1. The previously loaded
pointer settings are then used for the readback operation.
DACD
X
LSB
MSB
DACC DACB DACA
00
02066-031
Figure 31. Pointer Byte
POINTER BYTE BITS
Table 6 describes the individual bits that make up the pointer byte.
Table 6. Pointer Byte Bits
Bit
Description
X
Don’t care bits.
0
Reserved bits. Must be set to 0.
DACD
1: The following data bytes are for DAC D.
DACC
1: The following data bytes are for DAC C.
DACB
1: The following data bytes are for DAC B.
DACA
1: The following data bytes are for DAC A.
INPUT SHIFT REGISTER
The input shift register is 16 bits wide. Data is loaded into the
device as two data bytes on the serial data line, SDA, under the
control of the serial clock input, SCL. The timing diagram for
this operation is shown in Figure 2. The two data bytes consist
of four control bits followed by 8, 10, or 12 bits of DAC data,
depending on the device type. The first bits loaded are the
control bits: GAIN, BUF, CLR, and PD; the remaining bits are
left-justified DAC data bits, starting with the MSB (see Figure 32).
Table 7. Input Shift Register Control Bits
Bit
Description
GAIN
0: Output range for that DAC set at 0 V to VREF.
1: Output range for that DAC set at 0 V to 2 VREF.
BUF
0: Reference input for that DAC is unbuffered.
1: Reference input for that DAC is buffered.
CLR
0: All DAC registers and input registers are filled with
0s on completion of the write sequence.
1: Normal operation.
PD
0: On completion of the write sequence, all four DACs
go into power-down mode. The DAC outputs enter a
high impedance state.
1: Normal operation.
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